Class 257/284 - Schottky gate in groove

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the MESFET has a groove in at least
No. of patents: 203
Last issue date: 03/27/2012

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Number	Title	Issue Date
8143655	Trench schottky barrier diode with differential oxide thickness A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination...	03/27/2012
8080836	Embedded semiconductor component A process is disclosed for in-situ fabricating a semiconductor component imbedded in a substrate. A substrate is ablated with a first laser beam to form a void therein. A first conductive element is formed in the void of the substrate with a second laser beam. A sem...	12/20/2011
7732842	Structure and method for forming a planar schottky contact A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a cond...	06/08/2010
7709864	High-efficiency Schottky rectifier and method of manufacturing same A rectifier device (10) comprising a multi-layer epitaxial film (12) and a rectifier and a transistor manufactured in the film (12), wherein the transistor is oriented vertically relative to the plane of the rectifier. The rectifier and transist...	05/04/2010
7705377	Field effect transistor comprising compound semiconductor A field effect transistor having a double recess structure, which minimizes an influence exerted on a channel region depending upon the surface state of an outer recess section. In the field effect transistor having such a double recess structure, an ohmic contact l...	04/27/2010
7692222	Atomic layer deposition in the formation of gate structures for III-V semiconductor A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric f...	04/06/2010
7355281	Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is ...	04/08/2008
7345350	Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and th...	03/18/2008
7339242	NAND-type flash memory devices and fabrication methods thereof In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interc...	03/04/2008
7332795	Dielectric passivation for semiconductor devices A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier lay...	02/19/2008
7326962	Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer...	02/05/2008
7312125	Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and...	12/25/2007
7264743	Fin structure formation A method for forming fin structures is provided. Sacrificial structures are provided on a substrate. Fin structures are formed on the sides of the sacrificial structures. The forming of the fin structures comprises a plurality of cycles, wherein each cycle comprises...	09/04/2007
7199408	Semiconductor multilayer structure, semiconductor device and HEMT device A semiconductor device includes an underlying layer made of a group-III nitride containing at least Al and formed on a substrate, and a group of stacked semiconductor layers including a first semiconductor layer made of a group-III nitride, preferably GaN, a second ...	04/03/2007
7187014	Semiconductor device and method for fabricating the same A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been for...	03/06/2007
7180078	Integrated planar ion traps An apparatus for an ion trap includes an electrically conductive substrate having top and bottom surfaces and having vias that cross from the top surface to the bottom surface. The apparatus includes a pair of planar first electrodes supported over said top surface ...	02/20/2007
7169666	Method of forming a device having a gate with a selected electron affinity A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the...	01/30/2007
7154153	Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the...	12/26/2006
7140680	Fold down seat lumbar support apparatus and method A fold down seat back has an ergonomic support device in it. A traction cable is operatively engaged at one end with the lumbar support device to actuate it. The fold down seat back includes a rotating cable tension unit and a fixed torsion bar. The rotating member ...	11/28/2006
7141464	Method of fabricating T-type gate Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the sec...	11/28/2006
7137664	Automatically actuating ergonomic support system for a fold down seat A fold down seat back or seat bottom has at least one ergonomic support device in it. A traction cable is operatively engaged at one end with the ergonomic support device to actuate it. The fold down seat back includes a rotating cable tension unit and a fixed torsi...	11/21/2006
7130212	Field effect device with a channel with a switchable conductivity A field effect device (2) includes a source electrode (14), a drain electrode (16), a channel (24) formed between the source electrode (14) and the drain electrode (16), and a gate electrode (22) separated from the ch...	10/31/2006
7109588	Method and apparatus for attaching microelectronic substrates and support members A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surf...	09/19/2006
7109548	Operating a memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the...	09/19/2006
7105875	Lateral power diodes A lateral power diodes with an optimal drift doping formed in widebandgap semiconductors like Silicon Carbide, Aluminum Nitride and Gallium Nitride and Diamond are provided with a voltage rating greater 200V. Contrary to conventional vertical design of power diodes,...	09/12/2006
7087958	Termination structure of DMOS device In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon l...	08/08/2006
7083232	Massage apparatus and method for lumbar support An ergonomic support mountable on various seat frames has a static portion with anchors and mounts. The mounts adapt to fix said static portion to varying seat frames. An active portion is operatively engaged with the anchors of the static portion such that the acti...	08/01/2006
7077476	Universal ergonomic support with self-contained actuator An ergonomic weight support device for a seat comprising a housing having a channel defined by at least one guide boss, an extending element having an unanchored weight supporting end and an engaged end slidingly disposed within the channel of said housing and an ac...	07/18/2006
7078743	Field effect transistor semiconductor device A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type Aly	07/18/2006
7074684	Elevated source drain disposable spacer CMOS In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and d...	07/11/2006
7075125	Power semiconductor device A power semiconductor device includes a first semiconductor layer of non-doped AlXGa1−XN (0≦X≦1), and a second semiconductor layer of non-doped or n-type AlYGa1−YN (0≦Y≦1, X	07/11/2006
7052087	Method and apparatus for a scissors ergonomic support A scissors lumbar support includes a hinge axle and two arms each having a forward portion and a rearward portion. The forward portions are lumbar support pads. At least one of the rearward portions of the arms are adapted to operatively engage a force applicator. E...	05/30/2006
7015519	Structures and methods for fabricating vertically integrated HBT/FET device Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for f...	03/21/2006
7005356	Schottky barrier transistor and method of manufacturing the same A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrysta...	02/28/2006
6998225	Method of producing compound semiconductor device A method of producing a compound semiconductor device using a lift-off process. The lift-off process includes forming a resist mask having an electrode opening on an active layer of a compound semiconductor that is on a substrate of a compound semiconductor; forming...	02/14/2006
6979607	Technique to control tunneling currents in DRAM capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped po...	12/27/2005
6971719	Clutch actuator surface apparatus and method A clutch actuator has a housing with a load bearing element disposed within it. A force application element disposed within the housing applies force to the load bearing element. A stop assembly includes a retaining stopper between the load bearing element and the f...	12/06/2005
6967360	Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel l...	11/22/2005
6957596	Apparatus and method for braking ergonomic support actuator A braking actuator for an ergonomic support is connected thereto by a Bowden cable. The actuator has a housing with pin slots, friction surfaces and a mount for a disk axle. A disk has frictional surfaces, holes with pin load edges, a Bowden cable wire seat that hol...	10/25/2005
6956239	Transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer...	10/18/2005

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Class 257/284 - Schottky gate in groove