Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 8188520 | Field effect transistor and method for fabricating the same A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky... | 05/29/2012 |
| 7419882 | Alignment mark and alignment method for the fabrication of trench-capacitor dram devices A small-size (w | 09/02/2008 |
| 7411226 | High electron mobility transistor (HEMT) structure with refractory gate metal An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEM... | 08/12/2008 |
| 7391087 | MOS transistor structure and method of fabrication An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or sili... | 06/24/2008 |
| 7342261 | Light emitting device A light emitting device includes a substrate having a patterned surface and formed with a plurality of spaced apart cavities, and an epitaxial layer formed on the patterned surface of the substrate, having a patterned surface that is in face-to-face contact with the... | 03/11/2008 |
| 7304335 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 12/04/2007 |
| 7270868 | Micromechanical component A component having a surface micromechanical structure containing both movable elements and immovable elements, and a method of manufacturing same are described. The surface micromechanical structure of the component is produced in a functional layer, which is conne... | 09/18/2007 |
| 7107195 | Method for passenger classification using a seat mat in the vehicle seat A method is proposed for passenger classification using a seat mat in a vehicle seat, that functions so as to determine the magnitude of a coherent area of active matrix elements. Using the active matrix elements, a seat profile is generated, it being determined, us... | 09/12/2006 |
| 7030506 | Mask and method for using the mask in lithographic processing A method and mask to improve measurement of alignment marks is disclosed. An exemplary embodiment of the invention includes a resist mask with a patterned alignment mark comprising an assemblage of features whose spacing is smaller than the wavelength of light used ... | 04/18/2006 |
| 7023099 | Wafer cleaning method and resulting wafer A method of removing organic particles from a registration mark on a semiconductor wafer. The method comprises providing a semiconductor wafer comprising at least one registration mark at least partially filled with organic particles. The at least one registration m... | 04/04/2006 |
| 7005755 | Semiconductor device and fabrication process thereof A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support subst... | 02/28/2006 |
| 6998679 | Semiconductor device and method of fabricating the same A semiconductor device includes a gate electrode on a semiconductor substrate, a source electrode and a drain electrode that are provided on the semiconductor substrate, the gate electrode being interposed between the source electrode and the drain electrode, an ins... | 02/14/2006 |
| 6979874 | Semiconductor device and method of manufacturing thereof A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impur... | 12/27/2005 |
| 6940090 | Wideband gap having a low on-resistance and having a high avalanche capability A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semiconductor layer. The second semiconductor layer is formed on the first... | 09/06/2005 |
| 6936907 | Lateral high-voltage semiconductor devices with surface covered by thin film of dielectric material with high permittivity This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films... | 08/30/2005 |
| 6933523 | Semiconductor alignment aid An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low level of reflectivity includes at least one layer of tiles located in... | 08/23/2005 |
| 6929987 | Microelectronic device fabrication method In a method of forming a semiconductor device with a first channel layer formed over a portion of a second channel layer, a portion of the second channel underlying the first channel is etched so as to form an overhanging ledge in the first channel, and then a metal... | 08/16/2005 |
| 6924516 | Semiconductor device A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel lay... | 08/02/2005 |
| 6906419 | Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier... | 06/14/2005 |
| 6844579 | Organic device including semiconducting layer aligned according to microgrooves of photoresist layer An organic device including a substrate or a dielectric layer; a photoresist layer formed on the substrate or dielectric layer, wherein the photoresist layer is provided with a plurality of microgrooves having an alignment direction; an organic semiconducting layer ... | 01/18/2005 |
| 6787826 | Heterostructure field effect transistor A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is f... | 09/07/2004 |
| 6780694 | MOS transistor A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrod... | 08/24/2004 |
| 6777722 | Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af... | 08/17/2004 |
| 6773935 | Confocal 3D inspection system and process A confocal three dimensional inspection system, and process for use thereof, allows for rapid inspecting of bumps and other three dimensional (3D) features on wafers, other semiconductor substrates and other large format micro topographies. The sensor eliminates out... | 08/10/2004 |
| 6768143 | Structure and method of making three finger folded field effect transistors having shared junctions An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the subs... | 07/27/2004 |
| 6753559 | Transistor having improved gate structure A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconducto... | 06/22/2004 |
| 6653667 | GaAs-based semiconductor field-effect transistor A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor ... | 11/25/2003 |
| 6613623 | High fMAX deep submicron MOSFET A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A f... | 09/02/2003 |
| 6570238 | Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shie... | 05/27/2003 |
| 6504190 | FET whose source electrode overhangs gate electrode and its manufacture method A gate electrode is in Schottky contact with the surface of a semiconductor substrate and extends in a first direction. A drain electrode is disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and is in ohmic... | 01/07/2003 |
| 6501146 | Semiconductor device and method of manufacturing thereof A plurality of p anode regions are formed at one surface of an n- substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a mini... | 12/31/2002 |
| 6483135 | Field effect transistor A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source el... | 11/19/2002 |
| 6448147 | Semiconductor device and method for manufacturing the same As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line... | 09/10/2002 |
| 6424005 | LDMOS power device with oversized dwell An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of t... | 07/23/2002 |
| 6384442 | Fabrication process for metal-insulator-metal capacitor with low gate resistance A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as Six | 05/07/2002 |
| 6323521 | Thin film transistor with electrodes having compressive and tensile stress A thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulating layer on the substrate and covering the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer and not over... | 11/27/2001 |
| 6258639 | Sintered gate schottky barrier fet passivated by a degradation-stop layer A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a ch... | 07/10/2001 |
| 6225653 | Semiconductor components and methods of manufacturing semiconductor components A semiconductor component (1a) has a highly-doped substrate (4) of a first type of doping into which a highly-doped layer (15) of a second type of doping is introduced in some areas to form a pn Zener junction (16), and a low-doped area (17) of the second... | 05/01/2001 |
| 6175134 | Thin film transistors A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus... | 01/16/2001 |
| 6147370 | Field effect transistor with first and second drain electrodes To enhance a drain current voltage characteristics of a compound semiconductor field effect transistor, an n-GaAs substrate is used. After forming an n- -GaAs layer and an i-AlGaAs layer successively on the substrate, an n-type transistor is fo... | 11/14/2000 |
