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| Number | Title | Issue Date |
| 7834344 | Nanometric structure and corresponding manufacturing method A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a ... | 11/16/2010 |
| 7834345 | Tunnel field-effect transistors with superlattice channels A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At le... | 11/16/2010 |
| 7718996 | Semiconductor device comprising a lattice matching layer A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The... | 05/18/2010 |
| 7692183 | Polarity inversion of type-II InAs/GaSb superlattice photodiodes The subject invention comprises the realization of P-on-N type II InAs/GaSb superlattice photodiodes. A high-quality InAsSb layer lattice-mismatched to GaSb is used as a buffer to prepare the surface of the substrate prior to superlattice growth. The InAsSb layer al... | 04/06/2010 |
| 7659539 | Semiconductor device including a floating gate memory cell with a superlattice channel A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on th... | 02/09/2010 |
| 7598517 | Superjunction trench device and method Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52- | 10/06/2009 |
| 7586116 | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, ... | 09/08/2009 |
| 7459720 | Single crystal wafer and solar battery cell The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of α (0° | 12/02/2008 |
| 7435988 | Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of ... | 10/14/2008 |
| 7417227 | Scanning interference electron microscope The conventional detection technique has the following problems in detecting interference fringes: (1) Setting and adjustment are complex and difficult to conduct; (2) A phase image and an amplitude image cannot be displayed simultaneously; and (3) Detection efficie... | 08/26/2008 |
| 7375368 | Superlattice for fabricating nanowires This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be cre... | 05/20/2008 |
| 7372565 | Spectrometer measurement of diffracting structures A normal incidence reflectometer includes a rotatable analyzer/polarizer for measurement of a diffracting structure. Relative rotation of the analyzer/polarizer with respect to the diffracting structure permits analysis of the diffracted radiation at multiple polari... | 05/13/2008 |
| 7365357 | Strain inducing multi-layer cap A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a laye... | 04/29/2008 |
| 7332765 | Variable resistance functional body and storage device A variable resistance functional body has an insulator interposed between a first electrode and a second electrode and interposed between a third electrode and a fourth electrode. The insulator contains a plurality of conductive particles. The conductive particles a... | 02/19/2008 |
| 7282761 | Semiconductor memory devices having offset transistors and methods of fabricating the same Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series wi... | 10/16/2007 |
| 7279701 | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plur... | 10/09/2007 |
| 7236244 | Alignment target to be measured with multiple polarization states An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns at multiple polarization states and comparing the resulting intensities of the polari... | 06/26/2007 |
| 7230705 | Alignment target with designed in offset An alignment target includes periodic patterns on two elements. The alignment target includes two locations, at least one of which has a designed in offset. In one embodiment, both measurement locations have a designed in offset of the same magnitude but opposite di... | 06/12/2007 |
| 7198832 | Method for edge sealing barrier films An edge-sealed, encapsulated environmentally sensitive device. The device includes at least one initial barrier stack, an environmentally sensitive device, and at least one additional barrier stack. The barrier stacks include at least one decoupling layer and at lea... | 04/03/2007 |
| 7189660 | Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic laye... | 03/13/2007 |
| 7141807 | Nanowire capillaries for mass spectrometry A capillary for a mass spectrometry system is described. The capillary comprises a channel and a tip, and at least one of the channel and the tip comprises a nanowire material. ... | 11/28/2006 |
| 7129458 | Image pickup device, radiation image pickup device and image processing system An image pickup device has a plurality of photoelectric converter substrates carrying respective input/output terminals connected to the photoelectric converters. The device comprises leads connected to the input/output terminals and extending to the side opposite t... | 10/31/2006 |
| 7115858 | Apparatus and method for the measurement of diffracting structures A normal incidence reflectometer includes a rotatable analyzer/polarizer, which permits measurement of a diffracting structure. Relative rotation of the analyzer/polarizer with respect to the diffracting structure permits analysis of the diffracted radiation at mult... | 10/03/2006 |
| 7102145 | System and method for improving spatial resolution of electron holography A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident par... | 09/05/2006 |
| 7061014 | Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film Disclosed is a natural-superlattice homologous single-crystal thin film, which includes a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of th... | 06/13/2006 |
| 7061615 | Spectroscopically measured overlay target An overlay target for spectroscopic measurement includes at least two diffraction gratings, one grating overlying the other. The diffraction gratings may include an asymmetry relative to each other in order to improve resolution of the presence as well as the direct... | 06/13/2006 |
| 7038234 | Thermoelectric module with Si/SiGe and B4C/B9C super-lattice legs A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon... | 05/02/2006 |
| 7023010 | Si/C superlattice useful for semiconductor devices A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are... | 04/04/2006 |
| 7009224 | Metamorphic long wavelength high-speed photodiode A metamorphic device including a substrate structure upon which a semiconductor device can be formed. In the metamorphic device, a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading layer which grades past t... | 03/07/2006 |
| 6998306 | Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transist... | 02/14/2006 |
| 6992764 | Measuring an alignment target with a single polarization state An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns with an incident beam having a single polarization state and detecting the intensity ... | 01/31/2006 |
| 6965107 | Semiconductor-based encapsulated infrared sensor and electronic device An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into t... | 11/15/2005 |
| 6949462 | Measuring an alignment target with multiple polarization states An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns at multiple polarization states and comparing the resulting intensities of the polari... | 09/27/2005 |
| 6914008 | Structure having pores and its manufacturing method A structure having pores includes a first layer containing alumina, a second layer that includes at least one of Ti, Zr, Hf, Nb, Ta, Mo, W and Si, and a third layer with electrical conductivity, in this order, wherein the first and second layers have pores. ... | 07/05/2005 |
| 6914256 | Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically ... | 07/05/2005 |
| 6900479 | Stochastic assembly of sublithographic nanoscale interfaces A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows ... | 05/31/2005 |
| 6900466 | Semiconductor component for generating polychromatic electromagnetic radiation A semiconductor component for generating a polychromatic electromagnetic radiation has a semiconductor chip with a first semiconductor layer and a second semiconductor layer, which is provided adjacent to the first semiconductor layer and has an electroluminescent r... | 05/31/2005 |
| 6897472 | Semiconductor device including MOSFET having band-engineered superlattice A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally... | 05/24/2005 |
| 6866901 | Method for edge sealing barrier films An edge-sealed barrier film composite. The composite includes a substrate and at least one initial barrier stack adjacent to the substrate. The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer. One of the barri... | 03/15/2005 |
| 6849868 | Methods and apparatus for resistance variable material cells The present invention is related to methods and apparatus to produce a memory cell or resistance variable material with improved data retention characteristics and higher switching speeds. In a memory cell according to an embodiment of the present invention, silver ... | 02/01/2005 |
