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| Number | Title | Issue Date |
| 7829919 | Semiconductor device A semiconductor device which can prevent peeling off of a gate electrode is provided. The semiconductor device has GaN buffer layer 12 formed on substrate 11, undoped AlGaN layer 13 formed on this buffer layer 12, drain electrode 16 | 11/09/2010 |
| 7635882 | Logic switch and circuits utilizing the switch A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. ... | 12/22/2009 |
| 7554138 | Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method including having a thin delta profile layer of germanium close to the bottom of the strained layer The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor l... | 06/30/2009 |
| 7531854 | Semiconductor device having strain-inducing substrate and fabrication methods thereof A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from t... | 05/12/2009 |
| 7345329 | Method for reduced N+ diffusion in strained Si on SiGe substrate The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N typ... | 03/18/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7297580 | Methods of fabricating transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 11/20/2007 |
| 7235862 | Gate-enhanced junction varactor A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. ... | 06/26/2007 |
| 7211861 | Insulated gate semiconductor device An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate l... | 05/01/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7179731 | Hypercontacting The invention, called hypercontacting, achieves a very high level of activated doping at an exposed surface region of a compound semiconductor. This enables production of low resistance ohmic contacts by creating a heavily doped region near the contact. Such region ... | 02/20/2007 |
| 7116567 | GaN semiconductor based voltage conversion device A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected acros... | 10/03/2006 |
| 7109100 | Semiconductor device and method for manufacturing semiconductor device To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer... | 09/19/2006 |
| 7081663 | Gate-enhanced junction varactor with gradual capacitance variation A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-po... | 07/25/2006 |
| 7078787 | Design and operation of gate-enhanced junction varactor with gradual capacitance variation A semiconductor junction varactor is designed with gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing... | 07/18/2006 |
| 7056779 | Semiconductor power device A p type base layer is formed in one surface region of an n type base layer. An n type emitter layer is formed in a surface region of the p type base layer. An emitter electrode is formed on the n type emitter layer and the p type base layer. A trench is formed in t... | 06/06/2006 |
| 7037785 | Method of manufacturing flash memory device Disclosed is a method of manufacturing the flash memory device. The method comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon film and a hard mask film on a semiconductor substrate, etching portions of the hard mask film, the first ... | 05/02/2006 |
| 7026797 | Extremely high-speed switchmode DC-DC converters Switchmode DC—DC power converters using one or more non-Silicon-based switching transistors and a Silicon-based (e.g. CMOS) controller are disclosed. The non-Silicon-based switching transistors may comprise, but are not necessarily limited to, III-V compound semic... | 04/11/2006 |
| 7026669 | Lateral channel transistor A lateral channel transistor with an optimal conducting channel formed in widebandgap semiconductors like Silicon Carbide and Diamond is provided. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports ... | 04/11/2006 |
| 7015519 | Structures and methods for fabricating vertically integrated HBT/FET device Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for f... | 03/21/2006 |
| 6969627 | Light-emitting diode and the manufacturing method of the same The specification discloses a light-emitting diode and the corresponding manufacturing method. A GaN thick film with a slant surface is formed on the surface of a substrate. An epitaxial slant surface is naturally formed using the properties of the GaN epitaxy. An L... | 11/29/2005 |
| 6956239 | Transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 10/18/2005 |
| 6946717 | High voltage semiconductor device A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coup... | 09/20/2005 |
| 6924516 | Semiconductor device A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel lay... | 08/02/2005 |
| 6906350 | Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain... | 06/14/2005 |
| 6833571 | Transistor device including buried source A transistor device includes a gate region disposed adjacent to a semiconductor substrate such that a low impedance channel is formed between a source region and drain region of a transistor device when a voltage is applied to its gate. The drain region of the devic... | 12/21/2004 |
| 6768146 | III-V nitride semiconductor device, and protection element and power conversion apparatus using the same A GaN-based Schottky diode includes a sapphire substrate on which are formed a GaN buffer layer, an n+-type GaN layer, and an n-type GaN layer that has a surface portion thereof shaped to form a protrusion having an upper face with which a Ti electrode fo... | 07/27/2004 |
| 6740911 | α-WO3-gate ISFET devices and method of making the same Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solutio... | 05/25/2004 |
| 6734476 | Semiconductor devices having group III-V compound layers A power semiconductor device includes a substrate of first conductivity having a dopant concentration of a first level. The substrate is a group III-V compound material. A transitional layer of first conductivity is epitaxially grown over the substrate. The transiti... | 05/11/2004 |
| 6670658 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type ... | 12/30/2003 |
| 6495871 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type ... | 12/17/2002 |
| 6492674 | Semiconductor device having an improved plug structure and method of manufacturing the same A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects a pair of active regions of the semiconductor elements for... | 12/10/2002 |
| 6465834 | Semiconductor device In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output v... | 10/15/2002 |
| 6429471 | Compound semiconductor field effect transistor and method for the fabrication thereof Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of... | 08/06/2002 |
| 6384428 | Silicon carbide semiconductor switching device The present semiconductor switching device comprises a silicon carbide single crystal of hexagonal symmetry having a first conductive type and a semiconductor region of a second conductive type opposite to the first conductive type and locating in the sil... | 05/07/2002 |
| 6365919 | Silicon carbide junction field effect transistor A lateral silicon carbide junction field effect transistor has p-conductive and n-conductive silicon carbide layers. The layers are provided in pairs in lateral direction in a silicon carbide body. Trenches for a source, a drain and a gate extend from a p... | 04/02/2002 |
| 6313482 | Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped s... | 11/06/2001 |
| 6303947 | Silicon carbide vertical FET and method for manufacturing the same A silicon carbide vertical field-effect transistor is provided wherein a first conductivity type drift layer formed of silicon carbide is laminated on a first conductivity type silicon carbide drain layer, and a second conductivity type gate region and a ... | 10/16/2001 |
| 6285046 | Controllable semiconductor structure with improved switching properties The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the sourc... | 09/04/2001 |
| 6278144 | Field-effect transistor and method for manufacturing the field effect transistor A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contac... | 08/21/2001 |
