Quotables
"The horse is here to stay, the automobile is only a novelty - fad."
President of Michigan Savings Bank ; 1903
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8148759 | Single transistor memory with immunity to write disturb Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide c... | 04/03/2012 |
| 8089108 | Double-gated transistor memory Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR... | 01/03/2012 |
| 8053819 | Three-dimensional cascaded power distribution in a semiconductor device An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage ... | 11/08/2011 |
| 7982250 | Semiconductor device A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semi... | 07/19/2011 |
| 7898009 | Independently-double-gated transistor memory (IDGM) Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR... | 03/01/2011 |
| 7795651 | One transistor DRAM device and method of forming the same A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body ... | 09/14/2010 |
| 7763915 | Three-dimensional integrated C-MOS circuit and method for producing same The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are fo... | 07/27/2010 |
| 7671389 | SRAM devices having buried layer patterns An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peri... | 03/02/2010 |
| 7525137 | TFT mask ROM and method for making same There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs. ... | 04/28/2009 |
| 7479673 | Semiconductor integrated circuits with stacked node contact structures Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a ... | 01/20/2009 |
| 7423304 | Optimization of critical dimensions and pitch of patterned features in and above a substrate A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver cir... | 09/09/2008 |
| 7402854 | Three-dimensional cascaded power distribution in a semiconductor device An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage ... | 07/22/2008 |
| 7394128 | Semiconductor memory device with channel regions along sidewalls of fins A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of ... | 07/01/2008 |
| 7388277 | Chip and wafer integration process using vertical connections A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrat... | 06/17/2008 |
| 7369424 | Programmable memory cell and operation method A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row line... | 05/06/2008 |
| 7369436 | Vertical NAND flash memory device Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND... | 05/06/2008 |
| 7365392 | Semiconductor device with integrated trench lateral power MOSFETs and planar devices Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same... | 04/29/2008 |
| 7352603 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 04/01/2008 |
| 7312487 | Three dimensional integrated circuit A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel an... | 12/25/2007 |
| 7298638 | Operating an electronic device having a vertical gain cell that includes vertical MOS transistors A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the se... | 11/20/2007 |
| 7288821 | Structure and method of three dimensional hybrid orientation technology A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direc... | 10/30/2007 |
| 7288823 | Double gate field effect transistor and method of manufacturing the same Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by a... | 10/30/2007 |
| 7280381 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 10/09/2007 |
| 7280382 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 10/09/2007 |
| 7259052 | Manufacture of a semiconductor integrated circuit device including a pluarality of a columnar laminates having different spacing in different directions For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X ... | 08/21/2007 |
| 7250646 | TFT mask ROM and method for making same There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs. ... | 07/31/2007 |
| 7244977 | Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory d... | 07/17/2007 |
| 7242059 | Semiconductor device having DMOS and CMOS on single substrate A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a ... | 07/10/2007 |
| 7226871 | Method for forming a silicon oxynitride layer A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide laye... | 06/05/2007 |
| 7217658 | Process modulation to prevent structure erosion during gap fill High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the proc... | 05/15/2007 |
| 7190616 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 03/13/2007 |
| 7183197 | Water-barrier performance of an encapsulating film A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The mate... | 02/27/2007 |
| 7170726 | Uniform turn-on design on multiple-finger MOSFET for ESD protection application An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a... | 01/30/2007 |
| 7141856 | Multi-structured Si-fin Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produc... | 11/28/2006 |
| 7132701 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same con... | 11/07/2006 |
| 7130208 | Ferroelectric-type nonvolatile semiconductor memory A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode... | 10/31/2006 |
| 7119385 | Semiconductor apparatus having first and second gate electrodes A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocryst... | 10/10/2006 |
| 7110283 | Semiconductor memory device and semiconductor integrated circuit In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is ach... | 09/19/2006 |
| 7091604 | Three dimensional integrated circuits A three-dimensional integrated circuit that provides reduced interconnect signal delay over known 2-dimensional systems. The three-dimensional integrated circuit also allows improved circuit cooling. The three-dimensional integrated circuit includes two or more elec... | 08/15/2006 |
| 7030918 | Solid-state image pickup device The present invention discloses a solid-state image pickup device in which a photoelectric conversion part having a photoelectric conversion region, and a logic circuit part are formed on a semiconductor substrate, and outputs a potential change caused by the charge... | 04/18/2006 |
