Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7855404 | Bipolar complementary semiconductor device A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipol... | 12/21/2010 |
| 7582922 | Semiconductor device A semiconductor device is disclosed. One embodiment provides a top surface. A first lateral semiconductor region is arranged adjacent to the top surface and includes a transistor structure. The transistor structure includes a drain zone of a first conductivity type.... | 09/01/2009 |
| 7385231 | Porous thin-film-deposition substrate, electron emitting element, methods of producing them, and switching element and display element A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate ... | 06/10/2008 |
| 7378688 | Method and apparatus for a low noise JFET device on a standard CMOS process A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from on... | 05/27/2008 |
| 7365362 | Semiconductor device and method of fabricating semiconductor device using oxidation According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a gate insulating film on a semiconductor substrate; forming a film containing a predetermin... | 04/29/2008 |
| 7348611 | Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a ... | 03/25/2008 |
| 7345329 | Method for reduced N+ diffusion in strained Si on SiGe substrate The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N typ... | 03/18/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 12/25/2007 |
| 7233035 | Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the seco... | 06/19/2007 |
| 7223650 | Self-aligned gate isolation Embodiments of the invention include a circuit with a transistor having a self-aligned gate. Insulating isolation structures may be formed, self-aligned to diffusions. The gate may then be formed self-aligned to the insulating isolation structures. ... | 05/29/2007 |
| 7211513 | Process for chemical vapor desposition of a nitrogen-doped titanium oxide coating Nitrogen doped titanium oxide coatings on a hot glass substrate are prepared by providing a uniform vaporized reactant mixture containing a titanium compound, a nitrogen compound and an oxygen-containing compound, and delivering the reactant mixture to the surface o... | 05/01/2007 |
| 7202516 | CMOS transistor structure including film having reduced stress by exposure to atomic oxygen A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stre... | 04/10/2007 |
| 7193254 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the fi... | 03/20/2007 |
| 7180137 | Semiconductor device A terminating resistance element of an LSI chip has an N− type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N | 02/20/2007 |
| 7161216 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 01/09/2007 |
| 7144795 | Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 12/05/2006 |
| 7138311 | Semiconductor integrated circuit device and manufacture method therefore A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a ... | 11/21/2006 |
| 7135722 | Wiring layout of semiconductor device and design method of the same A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a ... | 11/14/2006 |
| 7095065 | Varying carrier mobility in semiconductor devices to achieve overall design goals A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A ... | 08/22/2006 |
| 7087942 | Semiconductor integrated circuit device with reduced leakage current The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage cur... | 08/08/2006 |
| 7081648 | Lossless co-planar wave guide in CMOS process A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four embodiments.... | 07/25/2006 |
| 7078747 | Semiconductor device having a HMP metal gate A semiconductor device has a dual-gate electrode structure. The gate electrode has a layered structure including a doped polysilicon film, WSi2 film, WN film and a W film. The WSi2 film formed on the polysilicon film in the P-channel area is fo... | 07/18/2006 |
| 6995432 | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent theret... | 02/07/2006 |
| 6984855 | Manufacturing method of semiconductor device and semiconductor device A semiconductor device comprising a buried insulating film formed in a substrate; a protective film formed on the buried insulating film covering corresponding diffusion regions of a P-type MISFET and a N-type MISFET, wherein the protective film is etch resistant to... | 01/10/2006 |
| 6974981 | Isolation structures for imposing stress patterns A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose... | 12/13/2005 |
| 6963134 | Semiconductor sensor with substrate having a certain electric potential A highly reliable semiconductor device less susceptible to external noise is provided. The semiconductor device has a signal output chip and a substrate. The signal output chip has one or more semiconductors and outputs a predetermined signal. The substrate has a ci... | 11/08/2005 |
| 6953729 | Heterojunction field effect transistor and manufacturing method thereof In a heterojunction FET in which source and drain areas are formed by carrying out high temperature annealing process after carrying out ion implantation in areas to be formed into source and drain areas, conventionally, the N-type carrier supply layer and the N-typ... | 10/11/2005 |
| 6906359 | BiFET including a FET having increased linearity and manufacturability According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch sto... | 06/14/2005 |
| 6894312 | EL display device Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110 | 05/17/2005 |
| 6885071 | Semiconductor integrated circuit making use of standard cells A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent st... | 04/26/2005 |
| 6841822 | Static random access memory cells A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transi... | 01/11/2005 |
| 6781155 | Electroluminescence display device with a double gate type thin film transistor having a lightly doped drain structure An organic EL display device including a first TFT (30) for switching operation, a second TFT (40) for driving an organic EL element, and an organic EL element (60) having an anode (61), a cathode (66), and a light emissive element... | 08/24/2004 |
| 6770921 | Sidewall strap for complementary semiconductor structures and method of making same Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two si... | 08/03/2004 |
| 6555839 | Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie... | 04/29/2003 |
| 6542001 | Power supply module in integrated circuits This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used a... | 04/01/2003 |
| 6515317 | Sidewall charge-coupled device with multiple trenches in multiple wells Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.... | 02/04/2003 |
| 6476430 | Integrated circuit In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD impla... | 11/05/2002 |
| 6384432 | Gallium antimonide complementary HFET A complementary heterojunction field effect transistor (CHFET) in which the channels for the p-FET device and the n-FET device forming the complementary FET are formed from gallium antimonide (GaSb) or indium antimonide (InSb). An n-type HFET structure is... | 05/07/2002 |
| 6344669 | CMOS sensor The present invention is about a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acting as a ph... | 02/05/2002 |
