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| Number | Title | Issue Date |
| 7633101 | Oxide isolated metal silicon-gate JFET A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, ga... | 12/15/2009 |
| 7538370 | Semiconductor device having reduced gate charge and reduced on resistance and method In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the f... | 05/26/2009 |
| 7531853 | Semiconductor device and manufacturing method of the same A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silic... | 05/12/2009 |
| 7528426 | Lateral junction field-effect transistor A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semi... | 05/05/2009 |
| 7485905 | Electrostatic discharge protection device An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finge... | 02/03/2009 |
| 7420232 | Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea... | 09/02/2008 |
| 7417266 | MOSFET having a JFET embedded as a body diode A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. ... | 08/26/2008 |
| 7411231 | JFET with drain and/or source modification implant The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would ot... | 08/12/2008 |
| 7378688 | Method and apparatus for a low noise JFET device on a standard CMOS process A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from on... | 05/27/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 12/25/2007 |
| 7286328 | Electrostatic discharge protection circuit for preamps connected to magneto-resistive read elements A magnetic storage system comprises a read element and an electrostatic discharge (ESD) protection circuit that includes a shunting device including a first terminal that communicates with a first terminal of the read element and a second terminal that communicates ... | 10/23/2007 |
| 7253071 | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer pr... | 08/07/2007 |
| 7238976 | Schottky barrier rectifier and method of manufacturing the same A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second do... | 07/03/2007 |
| 7227203 | Power system inhibit method and device and structure therefor A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is d... | 06/05/2007 |
| 7214991 | CMOS inverters configured using multiple-gate transistors An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to... | 05/08/2007 |
| 7091938 | Display device An EL display device free of a dispersion in the brightness caused by deterioration in the EL elements. The display device uses pixels of the current-controlled type to suppress a change in the current flowing through the EL elements caused by the deterioration in t... | 08/15/2006 |
| 7065162 | Method and system for down-converting an electromagnetic signal, and transforms for same Methods, systems, and apparatuses, and combinations and sub-combinations thereof, for down-converting an electromagnetic (EM) signal are described herein. Briefly stated, in embodiments the invention operates by receiving an EM signal and recursively operating on ap... | 06/20/2006 |
| 7049644 | Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea... | 05/23/2006 |
| 7023033 | Lateral junction field-effect transistor A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semi... | 04/04/2006 |
| 6960797 | Semiconductor device The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island... | 11/01/2005 |
| 6933569 | SOI MOSFET A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semicon... | 08/23/2005 |
| 6927460 | Method and structure for BiCMOS isolated NMOS transistor A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with ... | 08/09/2005 |
| 6927951 | Flex on suspension with dissipative polymer substrate acting as bleed resistor for minimizing ESD damage A head gimbal assembly that includes a bleed resistor applied over a specified area of the reader, writer and ground leads in order to protect from ESD damage is disclosed. The present invention address the need for an ESD protection system that includes a consisten... | 08/09/2005 |
| 6906359 | BiFET including a FET having increased linearity and manufacturability According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch sto... | 06/14/2005 |
| 6903426 | Semiconductor switching device A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 μm and a signal receiving FET has a gate width of 400 μm. A resistor conn... | 06/07/2005 |
| 6900482 | Semiconductor device having divided active regions with comb-teeth electrodes thereon A high-frequency semiconductor device for power amplification has a comb-teeth electrode on each of active regions formed on the front surface of the semiconductor substrate. One aspect of the present invention, there is provided a monolithic microwave integrated ci... | 05/31/2005 |
| 6885078 | Circuit isolation utilizing MeV implantation A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across t... | 04/26/2005 |
| 6777722 | Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af... | 08/17/2004 |
| 6768143 | Structure and method of making three finger folded field effect transistors having shared junctions An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the subs... | 07/27/2004 |
| 6710426 | Semiconductor device and transceiver apparatus A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate. In an embodiment of the invention, a metal insulator metal (MIM) cap... | 03/23/2004 |
| 6690040 | Vertical replacement-gate junction field-effect transistor A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of differ... | 02/10/2004 |
| 6661056 | DMOS transistor protected against polarity reversal The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrie... | 12/09/2003 |
| 6627973 | Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device A method of eliminating voids in the interlayer dielectric material of 0.18-μm flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric ... | 09/30/2003 |
| 6555857 | Semiconductor device The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substr... | 04/29/2003 |
| 6534807 | Local interconnect junction on insulator (JOI) structure A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, ... | 03/18/2003 |
| 6501110 | Semiconductor memory cell A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second re... | 12/31/2002 |
| 6476430 | Integrated circuit In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD impla... | 11/05/2002 |
| 6465830 | RF voltage controlled capacitor on thick-film SOI A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.... | 10/15/2002 |
| 6347050 | Semiconductor memory cell and method of manufacturing the same A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface regio... | 02/12/2002 |