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| Number | Title | Issue Date |
| 8169007 | Asymmetric junction field effect transistor A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and ... | 05/01/2012 |
| 7977714 | Wrapped gate junction field effect transistor A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second co... | 07/12/2011 |
| 7671387 | Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea... | 03/02/2010 |
| 7671388 | Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea... | 03/02/2010 |
| 7635881 | Continuous multigate transistors An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric l... | 12/22/2009 |
| 7605412 | Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do... | 10/20/2009 |
| 7569874 | Device and method of manufacture for a low noise junction field effect transistor A microelectronic product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from ... | 08/04/2009 |
| 7525136 | JFET device with virtual source and drain link regions and method of fabrication A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type... | 04/28/2009 |
| 7442590 | Method for forming a semiconductor device having a fin and structure thereof A method for forming a semiconductor device includes providing a semiconductor layer, forming a passivation layer over the semiconductor layer, wherein the passivation layer has an opening having sidewalls, forming a fin over the semiconductor layer, wherein after f... | 10/28/2008 |
| 7420232 | Lateral junction field effect transistor and method of manufacturing the same A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more hea... | 09/02/2008 |
| 7417270 | Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do... | 08/26/2008 |
| 7385249 | Transistor structure and integrated circuit A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedur... | 06/10/2008 |
| 7382662 | Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro... | 06/03/2008 |
| 7376403 | Terahertz radiation mixer A terahertz radiation mixer comprises a heterodyned field-effect transistor (FET) having a high electron mobility heterostructure that provides a gatable two-dimensional electron gas in the channel region of the FET. The mixer can operate in either a broadband pinch... | 05/20/2008 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte... | 04/01/2008 |
| 7348642 | Fin-type field effect transistor Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance bet... | 03/25/2008 |
| 7342264 | Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def... | 03/11/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7341916 | Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form... | 03/11/2008 |
| 7337547 | High frequency switching circuit device A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for swi... | 03/04/2008 |
| 7326976 | Corner dominated trigate field effect transistor Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing side... | 02/05/2008 |
| 7314787 | Method of manufacturing a semiconductor device A manufacturing method of a semiconductor device disclosed herein comprises: forming a convex first protrusion; forming a first film, of which a surface is higher than the first protrusion; forming a mask portion on the first film; and etching the first film with th... | 01/01/2008 |
| 7312486 | Stripe board dummy metal for reducing coupling capacitance Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of be... | 12/25/2007 |
| 7288805 | Double gate isolation A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a bur... | 10/30/2007 |
| 7276763 | Structure and method for forming the gate electrode in a multiple-gate transistor In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and... | 10/02/2007 |
| 7274053 | Fin device with capacitor integrated under gate electrode A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator c... | 09/25/2007 |
| 7262946 | Integrated electronic disconnecting circuits, methods, and systems Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blockin... | 08/28/2007 |
| 7262447 | Metal oxide silicon transistor and semiconductor apparatus having high λ and β performances A semiconductor apparatus includes a MOS transistor having a semiconductor substrate providing as a channel region between a source and a drain. A gate electrode is formed on the semiconductor substrate via a gate oxide film. A threshold voltage of the source side r... | 08/28/2007 |
| 7259425 | Tri-gate and gate around MOSFET devices and methods for making same A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gat... | 08/21/2007 |
| 7259984 | Multibit metal nanocrystal memories and fabrication Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid therm... | 08/21/2007 |
| 7221337 | Electro-luminescence display and drving method thereof An electro-luminescence display which obtains proper color realization even though identical data driving waveforms are applied to each group of R, G and B pixel cells. In the display, a plurality of data lines cross a plurality of gate lines to define a plurality o... | 05/22/2007 |
| 7214576 | Manufacturing method of semiconductor device A manufacturing method of a semiconductor device disclosed herein comprises: forming a first protrusion; forming a second protrusion which is higher than the first protrusion; forming a first sidewall on a side surface of the second protrusion; forming a first film ... | 05/08/2007 |
| 7202528 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 04/10/2007 |
| 7202521 | Silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on th... | 04/10/2007 |
| 7196374 | Doped structure for FinFET devices A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on... | 03/27/2007 |
| 7190009 | Semiconductor device There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate | 03/13/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7176067 | Methods of fabricating fin field effect transistors A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active reg... | 02/13/2007 |
| 7161197 | RF switching circuit for use in mobile communication systems An RF switching circuit according to the present invention includes: a plurality of input/output terminals for inputting and outputting an RF signal; and a switch for opening and closing an electrical connection between the input/output terminals. The switch is cons... | 01/09/2007 |
| 7141856 | Multi-structured Si-fin Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produc... | 11/28/2006 |
