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| Number | Title | Issue Date |
| 8159007 | Providing current to compensate for spurious current while receiving signals through a line Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sens... | 04/17/2012 |
| 8138529 | Package configurations for low EMI circuits An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The s... | 03/20/2012 |
| 7985991 | MOSFET package A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrod... | 07/26/2011 |
| 7504677 | Multi-gate enhancement mode RF switch and bias arrangement Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source... | 03/17/2009 |
| 7439563 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 10/21/2008 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7250643 | Semiconductor device and method of manufacturing the same A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source elect... | 07/31/2007 |
| 7232716 | Display device and method for manufacturing the same The average film thickness of an amorphous silicon film formed on a substrate is measured. Then, the amorphous silicon film is irradiated with a laser beam to form a polysilicon film, and the grain size distribution of the polysilicon film is measured. An optimum va... | 06/19/2007 |
| 7202528 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 04/10/2007 |
| 7173284 | Silicon carbide semiconductor device and manufacturing method A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer,... | 02/06/2007 |
| 7101436 | Crystallization apparatus, optical member for use in crystallization apparatus, crystallization method, manufacturing method of thin film transistor, and manufacturing method of matrix circuit substrate of display A crystallization apparatus includes an optical illumination system to illuminate a phase shift mask and which irradiates an amorphous semiconductor film with a light beam having an inverse peak type light intensity distribution including a minimum light intensity i... | 09/05/2006 |
| 7026668 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 04/11/2006 |
| 7023033 | Lateral junction field-effect transistor A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semi... | 04/04/2006 |
| 7011709 | Crystallization apparatus, optical member for use in crystallization apparatus, crystallization method, thin film transistor, and display A crystallization apparatus includes an illumination optical system to illuminate a phase shift mask and which irradiates an amorphous semiconductor film with a light beam having an intensity distribution of an inverse peak type having a smallest light intensity in ... | 03/14/2006 |
| 6989558 | Field effect transistor In a field effect transistor having an active region defined by a device isolation region, and a gate electrode formed over the active region, in the lateral direction of the gate electrode, the source and drain formed in the active region is narrower than the activ... | 01/24/2006 |
| 6952040 | Transistor structure and method of fabrication A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode... | 10/04/2005 |
| 6870189 | Pinch-off type vertical junction field effect transistor and method of manufacturing the same A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conduc... | 03/22/2005 |
| 6855970 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 02/15/2005 |
| 6777722 | Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af... | 08/17/2004 |
| 6690051 | FLASH memory circuitry FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH p... | 02/10/2004 |
| 6674145 | Flash memory circuitry A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches w... | 01/06/2004 |
| 6528405 | Enhancement mode RF device and fabrication method An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant area... | 03/04/2003 |
| 6521961 | Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-bar... | 02/18/2003 |
| 6368925 | Method of forming an EPI-channel in a semiconductor device An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is... | 04/09/2002 |
| 6307223 | Complementary junction field effect transistors Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally "off" JFETs, one in N-channel and one in P-channel to form Complementary Junction Fi... | 10/23/2001 |
| 6285046 | Controllable semiconductor structure with improved switching properties The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the sourc... | 09/04/2001 |
| 6172406 | Breakdown drain extended NMOS An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conduc... | 01/09/2001 |
| 6078094 | Starter current source device with automatic shut-down capability and method for its manufacture An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-ty... | 06/20/2000 |
| 5949095 | Enhancement type MESFET A carrier transfer layer of compound semiconductor material is disposed on or over a support substrate, and a gate electrode of conductive material is disposed on or over the carrier transfer layer at a partial region thereof. A cap layer of non-doped com... | 09/07/1999 |
| 5663589 | Current regulating semiconductor integrated circuit device and fabrication method of the same A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source... | 09/02/1997 |
| 5627387 | Overvoltage self-protection semiconductor device, method of fabrication thereof and semiconductor circuit using the same A novel semiconductor device with a pair of main surfaces is disclosed, in which at least three semiconductor layers are formed adjacently to each other. The device comprises a main thyristor portion for supplying a main current, an auxiliary thyristor po... | 05/06/1997 |
| 5612547 | Silicon carbide static induction transistor A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate... | 03/18/1997 |
| 5545905 | Static induction semiconductor device with a static induction schottky shorted structure The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main e... | 08/13/1996 |
| 5532511 | Semiconductor device comprising a highspeed static induction transistor A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of... | 07/02/1996 |
| 5424562 | Lateral static induction transistor A lateral static induction transistor suited for use as a picture element of a solid state imaging device. The lateral static induction transistor includes a semiconductor substrate of a first conduction type of P type or N type, a first epitaxial layer o... | 06/13/1995 |
| 5401987 | Self-cascoding CMOS device A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 vo... | 03/28/1995 |
| 5367186 | Bounded tub fermi threshold field effect transistor A Fermi-FET includes a Fermi-tub region at a semiconductor substrate surface, wherein the Fermi-tub depth is bounded between a maximum tub depth and a minimum tub depth. The Fermi-tub depth is sufficiently deep to completely deplete the Fermi-tub region b... | 11/22/1994 |
| 5338949 | Semiconductor device having series-connected junction field effect transistors A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused ... | 08/16/1994 |
| 5304822 | Static induction type semiconductor device with multiple source contact regions A static induction type semiconductor device of a surface gate type, includes a source region, gate region and drain region. A channel region is formed between the drain region and the source region, such that when a bias potential is applied between the ... | 04/19/1994 |
| 5194923 | Fermi threshold field effect transistor with reduced gate and diffusion capacitance An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the s... | 03/16/1993 |
