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| Number | Title | Issue Date |
| 8022394 | Molecular quantum interference apparatus and applications of same A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical con... | 09/20/2011 |
| 7910918 | Gated resonant tunneling diode A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require... | 03/22/2011 |
| 7893426 | Single-charge tunnelling device A single-electron transistor (1) has an elongate conductive channel (2) and a side gate (3) formed in a 5 nm-thick layer (4) of Ga0.98Mn0.02As. The single-electron transistor (1) is operable, in a first mode, ... | 02/22/2011 |
| 7638792 | Tunnel junction light emitting device A tunnel junction light emitting device according to the present invention is provided with an active layer and an electron tunneling region supplying the active layer with carriers. The electron tunneling region has a first p-type semiconductor layer, a second p-ty... | 12/29/2009 |
| 7579618 | Carbon nanotube resonator transistor and method of making same A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is cla... | 08/25/2009 |
| 7528403 | Hybrid silicon-on-insulator waveguide devices Device designs and techniques for providing efficient hybrid silicon-on-insulator devices where a silicon waveguide core or resonator is clad by the insulator and a top functional cladding layer in some implementations of the designs. ... | 05/05/2009 |
| 7442953 | Wavelength selective photonics device A device comprising a number of different wavelength-selective active-layers arranged in a vertical stack, having band-alignment and work-function engineered lateral contacts to said active-layers, consisting of a contact-insulator and a conductor-insulator. Photons... | 10/28/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7361943 | Silicon-based backward diodes for zero-biased square law detection and detector arrays of same A Si-based diode (10, 10′, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16′, 18, 18′, 30, 32, 160, 161) having a backward diode curre... | 04/22/2008 |
| 7358920 | Cavity embedded antenna A nested cavity embedded loop mode antenna is provided with an ultra wide band response by nesting individual embedded cavity meander line loaded antenna modules, with the meander lines coupled to a ground plane plate either capacitively or directly so as to provide... | 04/15/2008 |
| 7352542 | Enhanced spin-valve sensor with engineered overlayer formed on a free layer A GMR sensor is disclosed for sensing magnetically recorded information on a data storage medium. The sensor includes a ferromagnetic free layer and a ferromagnetic pinned layer sandwiching an electrically conductive spacer layer. An engineered overlayer is formed o... | 04/01/2008 |
| 7351996 | Method of increasing efficiency of thermotunnel devices The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted wi... | 04/01/2008 |
| 7351604 | Microstructures A method for forming a microstructures is described. The method comprises: depositing a seed material on a substrate; growing a nanotube from the seed material; depositing microstructure material on the substrate to embed the nanotube in the microstructure material;... | 04/01/2008 |
| 7336449 | Three terminal magnetic sensor (TTM) having a metal layer formed in-plane and in contact with the base region for reduced base resistance A three terminal magnetic sensor (TTM) has a base region, a collector region which is adjacent the base region, an emitter region, and a barrier region which separates the emitter region from the base region. A sensing plane is defined along sides of the base region... | 02/26/2008 |
| 7335908 | Nanostructures and methods for manufacturing the same A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.... | 02/26/2008 |
| 7329606 | Semiconductor device having nanowire contact structures and method for its fabrication A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a dop... | 02/12/2008 |
| 7330620 | Low loss funnel-type PLC optical splitter with input cladding mode absorption structure and/or output segmented taper structure A funnel-type planar lightwave circuit (PLC) optical splitter having an input optical waveguide, a slab waveguide receiving the input optical signal from the input optical waveguide, and output waveguides projecting from the slab region. The region connecting the sl... | 02/12/2008 |
| 7327037 | High density nanostructured interconnection A method and apparatus for forming an electrically and/or thermally conducting interconnection is disclosed wherein a first surface and a second surface are contacted with each other via a plurality of nanostructures disposed on at least one of the surfaces. In one ... | 02/05/2008 |
| 7317230 | Fin FET structure A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby r... | 01/08/2008 |
| 7317436 | Liquid crystal display device and method of fabricating the same A liquid crystal display device includes a liquid crystal display panel having an effective area and a non-display area, and a temperature sense pattern provided within the non-display area of the liquid crystal display panel. ... | 01/08/2008 |
| 7303948 | Semiconductor device including MOSFET having band-engineered superlattice A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally... | 12/04/2007 |
| 7301199 | Nanoscale wires and related devices The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be singl... | 11/27/2007 |
| 7295586 | Carbon doped GaAsSb suitable for use in tunnel junctions of long-wavelength VCSELs GaAs(1−x)Sbx layers are grown by MOCVD. For lattice matching with InP, x is set to 0.5, while beneficial alternatives include setting x to 0.23, 0.3, and 0.4. During MOVCD, TMGa (or TEGa), TMSb, and AsH3 (or TBAs) are used to fabri... | 11/13/2007 |
| 7294248 | Fabrication and activation processes for nanostructure composite field emission cathodes A method of forming an electron emitter includes the steps of: (i) forming a nanostructure-containing material; (ii) forming a mixture of nanostructure-containing material and a matrix material; (iii) depositing a layer of the mixture onto at least a portion of at l... | 11/13/2007 |
| 7288457 | Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain r... | 10/30/2007 |
| 7279699 | Integrated circuit comprising a waveguide having an energy band engineered superlattice An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stac... | 10/09/2007 |
| 7279701 | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plur... | 10/09/2007 |
| 7276172 | Method for preparing a nanowire crossbar structure and use of a structure prepared by this method The present invention relates to a method for preparing a nanowire crossbar structure, comprising: (a) providing a substrate; (b) depositing thereon a composite structure comprising a nucleic acid-block copolymer having equidistant nucleic acid-catalyst binding site... | 10/02/2007 |
| 7269052 | Device selection circuitry constructed with nanotube technology A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nano... | 09/11/2007 |
| 7265002 | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of la... | 09/04/2007 |
| 7262075 | High-aspect-ratio metal-polymer composite structures for nano interconnects A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performa... | 08/28/2007 |
| 7253035 | Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer; forming a semiconductor layer; forming a lower data line; forming an upper data line including a source ele... | 08/07/2007 |
| 7230805 | Semiconductor slider with an integral spin valve transistor structure and method for making same without a bonding step A semiconductor slider including an integral spin valve transistor (SVT) having a read width of 250 nm or less disposed on a monolithic semiconductor. substrate, useful in magnetic data storage applications. The monolithic slider may also include other magnetic and ... | 06/12/2007 |
| 7229902 | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and ... | 06/12/2007 |
| 7227174 | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying lay... | 06/05/2007 |
| 7224174 | Optical alignment loops for the wafer-level testing of optical and optoelectronic chips This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. A wafer level test system uses an optical probe to search for and align with an optical alig... | 05/29/2007 |
| 7224041 | Design and fabrication of 6.1-Å family semiconductor devices using semi-insulating A1Sb substrate For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices whil... | 05/29/2007 |
| 7220636 | Process for controlling performance characteristics of a negative differential resistance (NDR) device A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation... | 05/22/2007 |
| 7221005 | Negative resistance field-effect device A negative resistance field-effect element that is a negative differential resistance field-effect element capable of achieving negative resistance at a low power supply voltage (low drain voltage) and also enabling securement of a high PVCR is formed on its InP sub... | 05/22/2007 |
| 7211821 | Devices with optical gain in silicon A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rar... | 05/01/2007 |
