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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 8053813 | Semiconductor device and layout method thereof A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement ord... | 11/08/2011 |
| 7915647 | Semiconductor integrated circuit A nonvolatile semiconductor memory concerning an example of the present invention comprises a cell array, a plurality of conducting wires extending from the cell array to a lead area, and a plurality of contact holes to arranged in the lead area so that a distance f... | 03/29/2011 |
| 7550790 | D/A conversion circuit and semiconductor device A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is conn... | 06/23/2009 |
| 7511318 | Electromechanical memory array using nanotube ribbons and method for making same Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports... | 03/31/2009 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7388260 | Structure for spanning gap in body-bias voltage routing structure Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. ... | 06/17/2008 |
| 7374986 | Method of fabricating field effect transistor (FET) having wire channels In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, t... | 05/20/2008 |
| 7368325 | Semiconductor package A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. ... | 05/06/2008 |
| 7368767 | Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a ... | 05/06/2008 |
| 7365377 | Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed i... | 04/29/2008 |
| 7365376 | Semiconductor integrated circuit A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power s... | 04/29/2008 |
| 7358549 | Multi-layered metal routing technique In accordance with the objectives of the invention a new method and structure is provided for the creation of multiple overlying layers of interconnect metal. A channel is reserved for the creation of via interconnects, no vias are placed on metal lines. The metal l... | 04/15/2008 |
| 7352048 | Integration of barrier layer and seed layer The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed laye... | 04/01/2008 |
| 7352201 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 04/01/2008 |
| 7345352 | Insulating tube, semiconductor device employing the tube, and method of manufacturing the same An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as ... | 03/18/2008 |
| 7335526 | Sensing system A ChemFET Sensing system is Described. ... | 02/26/2008 |
| 7332817 | Die and die-package interface metallization and bump design and arrangement A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein. ... | 02/19/2008 |
| 7332753 | Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc... | 02/19/2008 |
| 7332378 | Integrated circuit memory system with dummy active region An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming s... | 02/19/2008 |
| 7321139 | Transistor layout for standard cell with optimized mechanical stress effect A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate ... | 01/22/2008 |
| 7310793 | Interconnect lines with non-rectilinear terminations Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some... | 12/18/2007 |
| 7276928 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 10/02/2007 |
| 7274205 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 09/25/2007 |
| 7274204 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 09/25/2007 |
| 7274051 | Field effect transistor (FET) having wire channels and method of fabricating the same In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, t... | 09/25/2007 |
| 7265396 | Semiconductor device A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer ... | 09/04/2007 |
| 7259441 | Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolat... | 08/21/2007 |
| 7251157 | Semiconductor device Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory... | 07/31/2007 |
| 7247553 | Method of manufacturing a semiconductor device To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The... | 07/24/2007 |
| 7230286 | Vertical FET with nanowire channels and a silicided bottom contact A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source... | 06/12/2007 |
| 7227254 | Integrated circuit package A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channel... | 06/05/2007 |
| 7227202 | Semiconductor device and cell A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals ... | 06/05/2007 |
| 7217966 | Self-protecting transistor array A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating condit... | 05/15/2007 |
| 7218370 | Display device A gate line is severed before the gate line reaches an Output portion of a vertical driving circuit of a display device, and the separated gate lines are connected by a metal wiring in an upper layer. The gate line is, for example, made of molybdenum, chrome, a moly... | 05/15/2007 |
| 7206552 | Semiconductor switching device A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. The gate width of each FET is about 400 μm, and the maximum power required for the device operation is maintained by a lager... | 04/17/2007 |
| 7196370 | Nonvolatile semiconductor memory device having trench-type isolation region, and method of fabricating the same A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type is... | 03/27/2007 |
| 7196363 | Multilayer metal structure of supply rings with large parasitic capacitance A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed ... | 03/27/2007 |
| 7195933 | Semiconductor device having a measuring pattern and a method of measuring the semiconductor device using the measuring pattern A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrate... | 03/27/2007 |
| 7191423 | Method and apparatus for folding and laying out electronic circuit A method and apparatus folds a circuit having a plurality of transistors. The folding includes: (a) determining a number of folds to realize a desired layout of the circuit based on a netlist of the circuit, a folded circuit having a number of fingers corresponding ... | 03/13/2007 |
| 7183594 | Configurable gate array cell with extended poly gate terminal A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the gate array cell, the poly gate terminal, with at least one section, extends further than the doping zones ... | 02/27/2007 |
