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| Number | Title | Issue Date |
| 6916713 | Code implantation process The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline, with a cap layer formed on the top of the wordline. A dielectric laye... | 07/12/2005 |
| 6910201 | Custom clock interconnects on a standardized silicon platform A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of th... | 06/21/2005 |
| 6909117 | Semiconductor display device and manufacturing method thereof A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current sup... | 06/21/2005 |
| 6909146 | Bonded wafer with metal silicidation A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silico... | 06/21/2005 |
| 6906360 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a... | 06/14/2005 |
| 6900479 | Stochastic assembly of sublithographic nanoscale interfaces A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows ... | 05/31/2005 |
| 6894312 | EL display device Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110 | 05/17/2005 |
| 6890048 | Printhead and image printing apparatus This invention provides a printhead capable of decreasing the ON resistance value without increasing the heater board size in order to downsize the heater board, an image printing apparatus using the printhead, and a control method therefor. In the printhead, heater... | 05/10/2005 |
| 6885044 | Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided b... | 04/26/2005 |
| 6882957 | Method for calculating physical properties, physical properties calculating apparatus, and computer program product A physical properties calculating apparatus accepts inputs of material and thickness of an intermediate layer, accepts inputs of material and thickness of an outer layer, accepts inputs of material and thickness of an inner layer, accepts an input of outside air hum... | 04/19/2005 |
| 6881976 | Heterojunction BiCMOS semiconductor A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base stru... | 04/19/2005 |
| 6881989 | Semiconductor integrated circuit having high-density base cell array A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate ... | 04/19/2005 |
| 6878978 | CMOS performance enhancement using localized voids and extended defects The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and ... | 04/12/2005 |
| 6872990 | Layout method of semiconductor device A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first... | 03/29/2005 |
| 6864518 | Bit cells having offset contacts in a memory array According to one exemplary embodiment, a semiconductor data array comprises an active segment situated on a substrate. The semiconductor data array can be, for example, a ROM array. The semiconductor data array further comprises a first word line situated over the a... | 03/08/2005 |
| 6849947 | Semiconductor device and pattern layout method thereof The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode drivers and anode drivers. ... | 02/01/2005 |
| 6846709 | Vertical gate CMOS with lithography-independent gate length Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Vertical transistors are used frequently in the integrated circuit art. Accordingly, improved methods for their formation, which are not ... | 01/25/2005 |
| 6841832 | Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leak... | 01/11/2005 |
| 6838712 | Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adj... | 01/04/2005 |
| 6838711 | Power MOS arrays with non-uniform polygate length In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off a... | 01/04/2005 |
| 6825510 | Termination structure incorporating insulator in a trench A power semiconductor device 10 has increased breakdown voltage due to an oxide termination structure. A peripheral trench 58 is filled with a dielectric material, such as silicon dioxide. The trench extends below the P well 22 that includes the... | 11/30/2004 |
| 6818929 | Standard cell for plural power supplies and related technologies A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case wh... | 11/16/2004 |
| 6815278 | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI ... | 11/09/2004 |
| 6815737 | Method for selective trimming of gate structures and apparatus formed thereby A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surf... | 11/09/2004 |
| 6812506 | Polysilicon linewidth measurement structure with embedded transistor A semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the multiple parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias ext... | 11/02/2004 |
| 6812111 | Methods for fabricating MOS transistors with notched gate electrodes In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a heigh... | 11/02/2004 |
| 6812534 | Static semiconductor memory device An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon w... | 11/02/2004 |
| 6806514 | Modular digital pixel sensor system A digital pixel sensor-based modular digital imaging system includes several integrated circuit modules. At least one module includes an integrated circuit die having a digital pixel sensor array and a frame buffer, and at least one module includes an integrated cir... | 10/19/2004 |
| 6806517 | Flash memory having local SONOS structure using notched gate and manufacturing method thereof A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge ... | 10/19/2004 |
| 6803610 | Optimized memory cell physical arrangement A semiconductor circuit array comprises a plurality of repetitive circuit blocks. Each of the circuit blocks comprises a plurality of functional circuit segments. Each of the functional circuit segments is physically oriented in on of a plurality of predetermined or... | 10/12/2004 |
| 6803611 | Use of indium to define work function of p-type doped polysilicon The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon o... | 10/12/2004 |
| 6800882 | Multiple-bit memory latch cell for integrated circuit gate array A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel an... | 10/05/2004 |
| 6787823 | Semiconductor device having cell-based basic element aggregate having protruding part in active region A semiconductor intergrated circuit including p-type active regions and n-type active regions provided on a semiconductor substrate. Gate interconnect lines are arranged in a first predetermined direction on the p-type active regions and the n-type active regions. O... | 09/07/2004 |
| 6781155 | Electroluminescence display device with a double gate type thin film transistor having a lightly doped drain structure An organic EL display device including a first TFT (30) for switching operation, a second TFT (40) for driving an organic EL element, and an organic EL element (60) having an anode (61), a cathode (66), and a light emissive element... | 08/24/2004 |
| 6773972 | Memory cell with transistors having relatively high threshold voltages in response to selective gate doping A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor s... | 08/10/2004 |
| 6768143 | Structure and method of making three finger folded field effect transistors having shared junctions An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the subs... | 07/27/2004 |
| 6768144 | Method and apparatus for reducing leakage current in an SRAM array A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor ... | 07/27/2004 |
| 6765245 | Gate array core cell for VLSI ASIC devices A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at loc... | 07/20/2004 |
| 6762442 | Semiconductor device carrying a plurality of circuits A semiconductor device includes on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, where a plurality of logic circuits having the same functions or different functions are mounted in the act... | 07/13/2004 |
| 6762469 | High performance CMOS device structure with mid-gap metal gate High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices... | 07/13/2004 |
