Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 7365372 | Semiconductor device and method for manufacturing semiconductor device The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to eac... | 04/29/2008 |
| 7355218 | Semiconductor component with a MOS transistor The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as t... | 04/08/2008 |
| 7242061 | Semiconductor device The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an elem... | 07/10/2007 |
| 7226805 | Sequential lithographic methods to reduce stacking fault nucleation sites An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel... | 06/05/2007 |
| 7220636 | Process for controlling performance characteristics of a negative differential resistance (NDR) device A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation... | 05/22/2007 |
| 7109521 | Silicon carbide semiconductor structures including multiple epitaxial layers having sidewalls An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel... | 09/19/2006 |
| 7075708 | Top-pumped waveguide amplifier The present invention relates to a waveguide amplifier which is comprised of silica or silica-related material co-doped with silicon nanoclusters and rare earth elements, and more particularly, to a waveguide amplifier with higher efficiency enhanced by top-pumping ... | 07/11/2006 |
| 7042744 | Diode stack Hermetically sealed high-voltage assemblies are made up of series-connected diodes. Exposed tabs bonding adjacent diodes allow for greater thermal dissipation than previous products. This allows higher current-carrying capacity especially if used in oil. ... | 05/09/2006 |
| 7026642 | Vertical tunneling transistor The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may ... | 04/11/2006 |
| 6940104 | Cascaded diode structure with deep N-well and method for making the same A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well... | 09/06/2005 |
| 6906354 | T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath t... | 06/14/2005 |
| 6838360 | Non-volatile semiconductor memory with single layer gate structure A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via ... | 01/04/2005 |
| 6797992 | Apparatus and method for fabricating a high reverse voltage semiconductor device The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. ... | 09/28/2004 |
| 6734470 | Laterally varying multiple diodes A method for producing laterally varying multiple diodes and their device embodiment are presented herein. As demonstrated, multiple resonant tunneling diodes are fabricated together utilizing a single epitaxial structure. Shallow, ion-implanted regions having varyi... | 05/11/2004 |
| 6690030 | Semiconductor device with negative differential resistance characteristics A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or "thinned" at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon o... | 02/10/2004 |
| 6661035 | Laser device based on silicon nanostructures A silicon-based light-emitting device is described and comprises an active region, an excitation system which can bring about a condition of inversion of the population of carriers within the active region, and semi-reflective elements which can define a ... | 12/09/2003 |
| 6555440 | Process for fabricating a top side pitted diode device A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to th... | 04/29/2003 |
| 6515345 | Transient voltage suppressor with diode overlaying another diode for conserving space A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semico... | 02/04/2003 |
| 6507043 | Epitaxially-grown backward diode A method of epitaxially growing backward diodes as well as apparatus grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped la... | 01/14/2003 |
| 6410950 | Geometrically coupled field-controlled-injection diode, voltage limiter and freewheeling diode having the geometrically coupled field-controlled-injection diode A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentrat... | 06/25/2002 |
| 6342718 | Compact SRAM cell using tunnel diodes The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5... | 01/29/2002 |
| 6169298 | Semiconductor light emitting device with conductive window layer A semiconductor light emitting device, such as the light emitting diode (LED) or the laser diode (LD), having a structure in which a light emitting area is a double heterostructure or a multi-layer quantum well structure. The light emitting area is formed... | 01/02/2001 |
| 6163039 | Triangular-barrier optoelectronic switch A GaAs-InGaP triangular-barrier optoelectronic switch (TBOS) is disclosed, wherein two i-InGaP layers are formed on both sides of the p+ -GaAs layer in the conventional triangular-barrier structure. By introducing avalanche multiplication and c... | 12/19/2000 |
| 6049364 | Display panel and display device using the same A liquid crystal display panel includes a counter substrate having a counter electrode and a multi-layered dielectric film both formed thereon, and an array substrate formed with pixel electrodes and thin-film transistors serving as switching elements. A ... | 04/11/2000 |
| 5952683 | Functional semiconductor element with avalanche multiplication A functional semiconductor element, which is designed to perform an ultrafast amplifying, bistable, similar functional operation by initiating and stopping an avalanche multiplication in one of i-type layers of what is called a triangular barrier diode (T... | 09/14/1999 |
| 5936265 | Semiconductor device including a tunnel effect element A semiconductor device includes a semiconductor substrate having an element region on the main surface thereof, an element isolation region formed to surround the element region on the main surface of the semiconductor substrate, a gate electrode formed o... | 08/10/1999 |
| 5864152 | Semiconductor memory and method of writing, reading, and sustaining data A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emi... | 01/26/1999 |
| 5825049 | Resonant tunneling device with two-dimensional quantum well emitter and base layers A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation et... | 10/20/1998 |
| 5705827 | Tunnel transistor and method of manufacturing same The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction... | 01/06/1998 |
| 5686739 | Three terminal tunnel device Disclosed is a three terminal tunnel device exhibiting a tunneling of carriers in a forward direction. The device comprises an intrinsic semiconductor region, an n-type degenerate semiconductor source region abutting one side of the intrinsic semiconducto... | 11/11/1997 |
| 5589696 | Tunnel transistor comprising a semiconductor film between gate and source/drain A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left the... | 12/31/1996 |
| 5514882 | Bistable four layer device memory cell and method for storing and retrieving binary information A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in ... | 05/07/1996 |
| 5500541 | Semiconductor device having voltage sensing element A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input volta... | 03/19/1996 |
| 5486704 | Semiconductor device and electronic device by use of the semiconductor A semiconductor devive comprises; a collector region of first conductivity type; a base region of second conductivity type; an emitter region of the first conductivity type; a thin film provided on the emitter region and capable of flowing therein a tunnel current;... | 01/23/1996 |
| 5422496 | Interband single-electron tunnel transistor and integrated circuit An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental consti... | 06/06/1995 |
| 5412598 | Bistable four layer device, memory cell, and method for storing and retrieving binary information A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in ... | 05/02/1995 |
| 5373186 | Bipolar transistor with monoatomic base layer between emitter and collector layers A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type l... | 12/13/1994 |
| 5365083 | Semiconductor device of band-to-band tunneling type A semiconductor device of band-to-band tunneling type including a silicon substrate, a first gate electrode formed by a highly doped surface region of the silicon substrate, a first silicon oxide film formed on a surface of the surface region, a silicon t... | 11/15/1994 |
| 5258625 | Interband single-electron tunnel transistor and integrated circuit An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental consti... | 11/02/1993 |
| 5144390 | Silicon-on insulator transistor with internal body node to source node connection A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed... | 09/01/1992 |
