Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7931187 | Injection molded solder method for forming solder bumps on substrates A flexible unitary mask has a plurality of through holes. A substrate has a plurality of wettable pads in recessed regions defining volumes. The through holes are aligned with the wettable pads. Molten solder is directly injected through the through holes of the fle... | 04/26/2011 |
| 7845547 | Method for manufacturing a printed wiring board A method for manufacturing a printed wiring board having a bump. The method includes forming a solder-resist layer having a small-diameter aperture and a large-diameter aperture, each aperture exposing a respective conductive pad of the printed wiring board, and pri... | 12/07/2010 |
| 7419084 | Mounting method for surface-mount components on a printed circuit board A method for surface mount solder of a comparatively large component is provided wherein a first intermediate component is soldered to a printed wring board and a larger second component is positioned and soldered to the printed wiring board using the intermediate c... | 09/02/2008 |
| 7416106 | Techniques for creating optimized pad geometries for soldering A technique for processing a circuit board involves placing a mask layer on the circuit board, where the mask layer defines a set of pad profiles for a component mounting location. Each pad profile has a set of rounded corners. The technique further involves forming... | 08/26/2008 |
| 7357293 | Soldering an electronics package to a motherboard In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of... | 04/15/2008 |
| 7358174 | Methods of forming solder bumps on exposed metal pads A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrie... | 04/15/2008 |
| 7325716 | Dense intermetallic compound layer Apparatus and methods of fabricating a bump limiting metallization structure including a two-step bump reflow process that reduces intermetallic compound porosity, increases bump strength, improve die yield, and device reliability. The first step comprises annealing... | 02/05/2008 |
| 7258263 | Bipolar plate fabrication A method for making a current collector plate includes providing a first sheet of material having a first bonding face and a first outer face. A second sheet of material is provided having a second bonding face and a second outer face. A work area is defined on at l... | 08/21/2007 |
| 7252218 | Bipolar plate fabrication by roll bonding An anti-bonding material is placed in a desired pattern onto a first sheet of conductive material. A second sheet of conductive material is roll bonded with the first sheet of material. Fluid is injected between the bonded first and second sheets of material to expa... | 08/07/2007 |
| 7232755 | Process for fabricating pad frame and integrated circuit package A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed la... | 06/19/2007 |
| 7148715 | Systems and methods for testing microelectronic imagers and microfeature devices Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic d... | 12/12/2006 |
| 7124931 | Via heat sink material The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated. | 10/24/2006 |
| 7102230 | Circuit carrier and fabrication method thereof A circuit carrier adapted for a pin grid array (PGA) package is disclosed. The circuit carrier comprises a substrate, at least one pin pad, at least one solder mask layer, at least one solder layer, at least one pin and a fixing layer. The pin pad is disposed over t... | 09/05/2006 |
| 7064428 | Wafer-level package structure A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged... | 06/20/2006 |
| 7028881 | Method for providing removable weld backing Method for welding objects having limited backside access to a cavity behind a region to be welded. The method includes inserting a fugitive backing material in an installation state into a first portion of the cavity proximate the region to be welded and then trans... | 04/18/2006 |
| 7023088 | Semiconductor package, semiconductor device and electronic device An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is for... | 04/04/2006 |
| 7008817 | Method for manufacturing micro electro-mechanical systems using solder balls A method for manufacturing micro electro-mechanical systems includes forming an insulation layer on an upper surface of a semiconductor substrate, forming a structure layer on an upper surface of the insulation layer and etching the structure layer, forming an under... | 03/07/2006 |
| 7004375 | Pre-applied fluxing underfill composition having pressure sensitive adhesive properties The present invention relates to a pressure sensitive fluxing underfill composition that may be pre-applied to electronic components, such as CSP's, in order to increase the reliability of the component against mechanical stresses such as impact and bending. The com... | 02/28/2006 |
| 7004376 | Solder printing mask, wiring board and production method thereof, electrooptical apparatus and production method thereof and electronic device and production method thereof There is provided a mask for use in printing solder on a plurality of terminals formed on a substrate so as to correspond to a plurality of terminals of an IC package. The mask has openings through which the solder is applied, and the openings are larger than the te... | 02/28/2006 |
| 6994243 | Low temperature solder chip attach structure and process to produce a high temperature interconnection A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pur... | 02/07/2006 |
| 6966482 | Connecting structure of printed circuit boards Lands formed on a flexible printed circuit board are electrically connected with lands formed on a rigid printed circuit board through solder. At this point, solder resist is formed between neighboring two lands on the rigid printed circuit board, and is terminated ... | 11/22/2005 |
| 6960828 | Electronic structures including conductive shunt layers Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier... | 11/01/2005 |
| 6929981 | Package design and method of manufacture for chip grid array A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be ass... | 08/16/2005 |
| 6926190 | Integrated circuit assemblies and assembly methods A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, ... | 08/09/2005 |
| 6910615 | Solder reflow type electrical apparatus packaging having integrated circuit and discrete components In a solder reflow type building of modular electrical apparatus involving integrated circuit and discrete components, fabrication operations are arranged to include the providing of a general type series of steps for each component element involving a reflow or joi... | 06/28/2005 |
| 6902098 | Solder pads and method of making a solder pad A device including a first solder pad and a second solder pad comprised of a post-soldering alloy composition on a substrate is provided. The alloy composition comprises two or more elements, and the post soldering alloy composition of the first solder pad has diffe... | 06/07/2005 |
| 6896173 | Method of fabricating circuit substrate The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. T... | 05/24/2005 |
| 6871775 | Process for soldering and connecting structure A barrier metal layer is provided on at least one of two electrodes, with one formed on a substrate and the other connected to an electronic component, so as to coat a base material of the electrode, which base material is made of a material containing Cu. Soldering... | 03/29/2005 |
| 6843407 | Solder bump fabrication method and apparatus A solder bump fabrication method is disclosed. First, a printed circuit board, having a plurality of devices, is provided. A material is formed on the printed circuit board, and it is disposed between pins of the devices to prevent the devices from short-circuiting ... | 01/18/2005 |
| 6802445 | Cost effective substrate fabrication for flip-chip packages A new method is provided for the creation of high-accuracy and low-accuracy openings overlying points of electrical access over the surface of a semiconductor device supporting substrate. Openings are first created for access to the substrate followed by copper plat... | 10/12/2004 |
| 6772512 | Method of fabricating a flip-chip ball-grid-array package without causing mold flash A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in... | 08/10/2004 |
| 6739497 | SMT passive device noflow underfill methodology and structure An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. T... | 05/25/2004 |
| 6736306 | Semiconductor chip package comprising enhanced pads A semiconductor chip package includes a semiconductor chip mounted on a top surface of a substrate. A bottom surface of the substrate has ball pads. Bonding pads of the chip are electrically connected to the substrate. Enhanced pads, each having one or more dummy pa... | 05/18/2004 |
| 6732908 | High density raised stud microjoining system and methods of fabricating the same A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, so... | 05/11/2004 |
| 6719186 | Method and apparatus for end-to-end welding of lined pipe A weld shield device for facilitating end-to-end welding of two pipe segments having fiberglass liners. The weld shield device includes an insulation material applied about the outer surface of a sleeve body. The sleeve body helps establish a welding gap between the... | 04/13/2004 |
| 6715663 | Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is ... | 04/06/2004 |
| 6705512 | Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predeter... | 03/16/2004 |
| 6698648 | Method for producing solderable and functional surfaces on circuit carriers Process for the production of at least one solderable surface in selected solder regions and of at least one functional surface in function regions differing from the solder regions on circuit carriers provided as well as of corresponding circuit carriers... | 03/02/2004 |
| 6659334 | Method for forming end-face electrode There is provided a method for forming end-face electrodes in which the end-face electrode can be securely formed with solder at a position in which a side electrode is formed and it can be formed without being affected by a jig for fixing a solder solid.... | 12/09/2003 |
| 6634543 | Method of forming metallic z-interconnects for laminate chip packages and boards Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperat... | 10/21/2003 |
