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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 7371697 | Ion-assisted oxidation methods and the resulting structures Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over d... | 05/13/2008 |
| 7364990 | Epitaxial crystal growth process in the manufacturing of a semiconductor device First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown,... | 04/29/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7357873 | Polymide thin film self-assembly process The invention presents a novel polyimide-based thin film self-assembly technology, including five process steps described as follows: (1) deposits a sacrificial layer and a low-stress microstructure layer on a silicon substrate; (2) patterns and etches the low-stres... | 04/15/2008 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on... | 02/26/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7320734 | Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceil... | 01/22/2008 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7312148 | Copper barrier reflow process employing high speed optical annealing A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier met... | 12/25/2007 |
| 7303982 | Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 12/04/2007 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7294561 | Internal gettering in SIMOX SOI silicon substrates The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a sili... | 11/13/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7291360 | Chemical vapor deposition plasma process using plural ion shower grids A chemical vapor deposition process is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mu... | 11/06/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7267781 | Method of fabricating optical filters A method of fabricating optical filter is disclosed. The method includes providing the substrate and selectively etching the substrate to form a plurality of freestanding layers. A plurality of dielectric layers is disposed over an outer surface of each of the frees... | 09/11/2007 |
| 7268053 | Semiconductor wafer and a method for manufacturing a semiconductor wafer A semiconductor wafer includes (a) a first principal side and a second principal side opposite to each other, (b) a first bevel contour and a second bevel contour provided at an outer periphery of the first principal side and the second principal side, (c) a first r... | 09/11/2007 |
| 7262466 | Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a seco... | 08/28/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7258931 | Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations ... | 08/21/2007 |
| 7256075 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be fo... | 08/14/2007 |
| 7250359 | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer.... | 07/31/2007 |
| 7244474 | Chemical vapor deposition plasma process using an ion shower grid A chemical vapor deposition process is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural orifices oriented in a non-parallel direction r... | 07/17/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7242075 | Silicon wafers and method of fabricating the same By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. ... | 07/10/2007 |
| 7232743 | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or allo... | 06/19/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7223676 | Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silic... | 05/29/2007 |
| 7221038 | Method of fabricating substrates and substrates obtained by this method Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous ... | 05/22/2007 |
| 7202124 | Strained gettering layers for semiconductor processes A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over ... | 04/10/2007 |
| 7198974 | Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is... | 04/03/2007 |
| 7198992 | Method of manufacturing a semiconductor device comprising doping steps using gate electrodes and resists as masks The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semicon... | 04/03/2007 |
| 7195990 | Process for producing a photoelectric conversion device that includes using a gettering process A catalyst element remaining in a first semiconductor film subjected to a first heat treatment (crystallization) is moved and concentrated/collected by subjecting a second semiconductor film which is formed on the first semiconductor film and contains a rare gas ele... | 03/27/2007 |
| 7195993 | Methods of fabricating gallium nitride semiconductor layers by lateral growth into trenches A gallium nitride layer is laterally grown into a trench in the gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. At least one microelectronic device may then be formed in the lateral gallium nitride semiconductor layer. Dislocati... | 03/27/2007 |
| 7193294 | Semiconductor substrate comprising a support substrate which comprises a gettering site A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond e... | 03/20/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7192791 | Semiconductor wafer having an edge based identification feature A semiconductor wafer comprises a wafer formed of a semiconductor material having a peripheral edge portion and a repeating mark on the edge portion of the wafer to allow identification of the wafer. Also described is a method of identifying and tracking these semic... | 03/20/2007 |
| 7192844 | Glass-based SOI structures Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20... | 03/20/2007 |
