Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Application No. | Application Title | Issue Date |
| 20110314461 | IMPLEMENTING PARALLEL LOOPS WITH SERIAL SEMANTICS The present invention extends to methods, systems, and computer program products for implementing parallel loops with serial semantics. Embodiments of the invention provide a semantic transforms and codegen patterns that provide more efficient parallel loop implementati... | 12/22/2011 |
| 20110271265 | METHOD OF AUTOMATIC GENERATION OF EXECUTABLE CODE FOR MULTI-CORE PARALLEL PROCESSING A system, method and computer program product for optimizing the process of compilation of computer program code. The compiler transforms the program code written in a variety of languages and creates additional code performing parallel processing of program tasks on ta... | 11/03/2011 |
| 20110231830 | Loop Transformation for Computer Compiler Optimization A new computer-compiler architecture includes code analysis processes in which loops present in an intermediate instruction set are transformed into more efficient loops prior to fully executing the intermediate instruction set. The compiler architecture starts by gener... | 09/22/2011 |
| 20110225573 | Computation Reuse for Loops with Irregular Accesses A compiler selects a nested loop within software code that includes an outer loop and an inner loop. The outer loop includes an outer induction variable and the inner loop includes an inner induction variable. The compiler identifies a computation included in the nested... | 09/15/2011 |
| 20110225213 | LOOP CONTROL FLOW DIVERSION Loop control flow diversion supports thread synchronization, garbage collection, and other situations involving suspension of long-running loops. Divertible loops have a loop body, a loop top, an indirection cell containing a loop top address, and a loop jump instructio... | 09/15/2011 |
| 20110185347 | METHOD AND SYSTEM FOR EXECUTION PROFILING USING LOOP COUNT VARIANCE A method for executing a computer program involving obtaining a statement of the source code, where the statement comprises a method call, and where the source code is composed in a statically-typed programming language. The method also involves, upon entry into a loop ... | 07/28/2011 |
| 20110161923 | PREPARING NAVIGATION STRUCTURE FOR AN AUDIOVISUAL PRODUCT The system includes a command set defining a plurality of navigation commands for an audiovisual reproduction apparatus and a human-oriented scripting program for automatically authoring a navigation structure for use in a stand alone audiovisual product playable in the... | 06/30/2011 |
| 20110047534 | PROACTIVE LOOP FUSION OF NON-ADJACENT LOOPS WITH INTERVENING CONTROL FLOW INSTRUCTIONS A system and method for optimization of code with non-adjacent loops. A compiler builds a node tree, which is not a control flow graph, that represents parent-child relationships of nodes of a computer program. Each node represents a control flow statement or a straight... | 02/24/2011 |
| 20110029962 | VECTORIZATION OF PROGRAM CODE A method for vectorization of a block of code is provided. The method comprises receiving a first block of code as input; and converting the first block of code into at least a second block of code and a third block of code. The first block of code accesses a first set ... | 02/03/2011 |
| 20100318980 | STATIC PROGRAM REDUCTION FOR COMPLEXITY ANALYSIS Described is an analysis tool/techniques for determining the computational complexity of a computer program, including when the program includes procedures having nested loops and/or multi-path loops. First, multi-path loops are converted into code-fragments consisting ... | 12/16/2010 |
| 20100318979 | VECTOR ATOMIC MEMORY OPERATION VECTOR UPDATE SYSTEM AND METHOD A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which may have recurring data points. The equation is then repla... | 12/16/2010 |
| 20100257516 | LEVERAGING MULTICORE SYSTEMS WHEN COMPILING PROCEDURES A method, apparatus and program product are provided for parallelizing analysis and optimization in a compiler. A plurality of basic blocks and a subset of data points of a computer program is prepared for processing by a main thread selected from a plurality of hardwar... | 10/07/2010 |
| 20100235819 | ONE-PASS COMPILATION OF VIRTUAL INSTRUCTIONS In embodiments, prior to compilation into machine code, a preprocessor generates directives by processing a source code and/or bytecode representation of a program and/or selecting default directives. The preprocessor embeds the directives in a bytecode representation o... | 09/16/2010 |
| 20100218196 | SYSTEM, METHODS AND APPARATUS FOR PROGRAM OPTIMIZATION FOR MULTI-THREADED PROCESSOR ARCHITECTURES Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first cus... | 08/26/2010 |
| 20100205592 | CONTROL STRUCTURE REFINEMENT OF LOOPS USING STATIC ANALYSIS A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting c... | 08/12/2010 |
| 20100175056 | COMPILER APPARATUS WITH FLEXIBLE OPTIMIZATION A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” con... | 07/08/2010 |
| 20100146495 | METHOD AND SYSTEM FOR INTERPROCEDURAL PREFETCHING A computing system has an amount of shared cache, and performs runtime automatic parallelization wherein when a parallelized loop is encountered, a main thread shares the workload with at least one other non-main thread. A method for providing interprocedural prefetchin... | 06/10/2010 |
| 20100122069 | Macroscalar Processor Architecture A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and e... | 05/13/2010 |
| 20100070956 | METHODS AND APPARATUS FOR JOINT PARALLELISM AND LOCALITY OPTIMIZATION IN SOURCE CODE COMPILATION Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first cus... | 03/18/2010 |
| 20100023932 | Efficient Software Cache Accessing With Handle Reuse A mechanism for efficient software cache accessing with handle reuse is provided. The mechanism groups references in source code into a reference stream with the reference stream having a size equal to or less than a size of a software cache line. The source code is tra... | 01/28/2010 |
| 20100023700 | Dynamically Maintaining Coherency Within Live Ranges of Direct Buffers Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference ... | 01/28/2010 |
| 20090328020 | INTERFACE OPTIMIZATION IN A CLOSED SYSTEM Interface optimization is provided using a closed system in which all the individual software components in the system are known to the compiler at a single point in time. This knowledge enables significant opportunities to optimize the implementation of interfaces on a... | 12/31/2009 |
| 20090328021 | Multiversioning if statement merging and loop fusion In one embodiment of the invention, a method for fusing a first loop nested in a first IF statement with a second loop nested in a second IF statement without the use of modified and referenced (mod-ref) information to determine if certain conditional statements in the ... | 12/31/2009 |
| 20090288075 | PARALLELIZING NON-COUNTABLE LOOPS WITH HARDWARE TRANSACTIONAL MEMORY A system and method for speculatively parallelizing non-countable loops in a multi-threaded application. A multi-core processor receives instructions for a multi-threaded application. The application may contain non-countable loops. Non-countable loops have an iteration... | 11/19/2009 |
| 20090259828 | EXECUTION OF RETARGETTED GRAPHICS PROCESSOR ACCELERATED CODE BY A GENERAL PURPOSE PROCESSOR One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Port... | 10/15/2009 |
| 20090083724 | System and Method for Advanced Polyhedral Loop Transformations of Source Code in a Compiler A system and method for advanced polyhedral loop transformations of source code in a compiler are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for per... | 03/26/2009 |
| 20090077545 | PIPELINED PARALLELIZATION OF MULTI-DIMENSIONAL LOOPS WITH MULTIPLE DATA DEPENDENCIES A mechanism for folding all the data dependencies in a loop into a single, conservative dependence. This mechanism leads to one pair of synchronization primitives per loop. This mechanism does not require complicated, multi-stage compile time analysis. This mechanism co... | 03/19/2009 |
| 20090077544 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR OPTIMIZING EMULATION OF A SUSPECTED MALWARE A method, system and program product for optimizing emulation of a suspected malware. The method includes identifying, using an emulation optimizer tool, whether an instruction in a suspected malware being emulated by an emulation engine in a virtual environment signifi... | 03/19/2009 |
| 20090064119 | Systems, Methods, And Computer Products For Compiler Support For Aggressive Safe Load Speculation Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identif... | 03/05/2009 |
| 20090064120 | Method and apparatus to achieve maximum outer level parallelism of a loop In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algori... | 03/05/2009 |
| 20090055815 | Eliminate Maximum Operation in Loop Bounds with Loop Versioning A method and computer program product for eliminating maximum and minimum expressions within loop bounds are provided. A loop in a code is identified. The loop is determined to meet conditions, which require an upper loop bound and a lower loop bound to contain maximum ... | 02/26/2009 |
| 20080313621 | SCALAR CODE REDUCTION USING SHORTEST PATH ROUTING This document discusses, among other things, a system and method computing the shortest path expression in a loop having a plurality of expressions. Candidate expressions in the loop are identified and partitioned into sets. A cost matrix is computed as a function of th... | 12/18/2008 |
| 20080271005 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR REDUCING NUMBER OF EXCEPTION CHECKS Based on operations within an uncounted loop of source code, one or more calculations are generated for determining, at runtime, an expected number of iterations through which the uncounted loop can iterate before encountering an exception corresponding to at least one ... | 10/30/2008 |
| 20080263524 | Method and System for State Machine Translation A state machine program is generated from a state machine. The state machine has states, transitions and events. A basic structure for the state machine program is generated. The basic structure has therein a structure that operates in non-final states. A statement is g... | 10/23/2008 |
| 20080250401 | Tiling across loop nests with possible recomputation Described is a technology by which a series of loop nests corresponding to source code are detected by a compiler, with the series of loop nests tiled together, (thereby increasing the ratio of cache hits to misses in a multi-processor environment). The compiler transfo... | 10/09/2008 |
| 20080244549 | METHOD AND APPARATUS FOR EXPLOITING THREAD-LEVEL PARALLELISM According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by ov... | 10/02/2008 |
| 20080229298 | Compiler Method for Employing Multiple Autonomous Synergistic Processors to Simultaneously Operate on Longer Vectors of Data A compiler includes a mechanism for employing multiple synergistic processors to execute long vectors. The compiler receives a single source program. The compiler identifies vectorizable loop code in the single source program and extracts the vectorizable loop code from... | 09/18/2008 |
| 20080222623 | Efficient Code Generation Using Loop Peeling for SIMD Loop Code with Multiple Misaligned Statements An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then insert... | 09/11/2008 |
| 20080010635 | Method, Apparatus, and Program Product for Improving Branch Prediction in a Processor Without Hardware Branch Prediction but Supporting Branch Hint Instruction A compiler includes a mechanism for improving branch prediction in a processor that supports a branch hint instruction. The compiler receives a sequence of instructions, wherein the sequence of instructions comprises a loop. This loop sequence employs an hbr instruction... | 01/10/2008 |
| 20070169019 | Hiding irrelevant facts in verification conditions A program verification process begins by converting a language of the program from a first language into an intermediate language representation. The loops of the program are eliminated. The program is converted from the intermediate language representation into a passi... | 07/19/2007 |
