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| Application No. | Application Title | Issue Date |
| 20120110561 | STRUCTURE LAYOUT OPTIMIZATIONS More effective compiler optimizations provide improved cache utilization. The compiler optimizations include a structure layout optimization that leaves the physical layout of the structure fields intact and instead changes the access order to these fields. The compiler... | 05/03/2012 |
| 20120084763 | IDENTIFYING CODE THAT WASTES TIME SWITCHING TASKS A method of detecting portions of code of a computer program that protect resources of a computer system unnecessarily can include identifying threads and synchronization objects that are used by a computer program during execution, determining the number of threads tha... | 04/05/2012 |
| 20120084762 | FINE-GRAINED PERFORMANCE CONFIGURATION OF APPLICATION A method, system and computer program product for performance configuration of an application by setting at least one performance preference for a performance-sensitive class in the application, specifying performance preference propagation policy of the class in the ap... | 04/05/2012 |
| 20120047496 | SYSTEM AND METHOD FOR REFERENCE-COUNTING WITH USER-DEFINED STRUCTURE CONSTRUCTORS A system is provided that includes a code-processing portion, an initializing-processing portion, an ID-processing portion, a request-processing portion and a compiling-processing portion. The code-processing portion can embed a code architecture into user-defined data ... | 02/23/2012 |
| 20120042306 | COMPILING SYSTEM AND METHOD FOR OPTIMIZING BINARY CODE A compiling system and method for optimizing binary code. The method includes the step of replacing a memory access on a stack area in order to save a value of a register with local variable access. The method further includes: giving a call number to a call instruction... | 02/16/2012 |
| 20120030518 | LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch w... | 02/02/2012 |
| 20120030659 | CONSTRUCTING RUNTIME STATE FOR INLINED CODE Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at whi... | 02/02/2012 |
| 20120017204 | STRING CACHE FILE FOR OPTIMIZING MEMORY USAGE IN A JAVA VIRTUAL MACHINE A method, system and computer program product for optimizing memory usage associated with duplicate string objects in a Java virtual machine. The method comprises scanning a heap of the Java virtual machine at the end of the start-up process of the virtual machine to id... | 01/19/2012 |
| 20110320786 | Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the curre... | 12/29/2011 |
| 20110314460 | COMPILE TIME INTERPRETATION OF MARKUP CODES The present invention extends to methods, systems, and computer program products for compile time interpretation of markup codes. Embodiments of the invention can be used to specify custom behaviors to be taken in response to any of a number of ways that markup codes (e... | 12/22/2011 |
| 20110314459 | COMPILER WITH USER-DEFINED TYPE INFERENCE RULES Performance of a program written in dynamic languages is improved through the use of a compiler that provides type inference for methods having a user-defined element. The user-defined element may be an input in a user-defined type. Though, the user-defined element may ... | 12/22/2011 |
| 20110307875 | TRACKING VARIABLE INFORMATION IN OPTIMIZED CODE Embodiments are directed to tracking variable location information in optimized code and efficiently collecting and storing reaching definition information. A computer system receives a portion of source code at a compiler, where the compiler is configured to compile an... | 12/15/2011 |
| 20110296389 | Mechanism for Allocating Statement Frontier Annotations to Source Code Statements A mechanism for allocating statement frontier annotations to source code statements of a software program is disclosed. A method of embodiments of the invention includes generating statement frontier annotations during translation of source code statements of a software... | 12/01/2011 |
| 20110289485 | Software Trace Collection and Analysis Utilizing Direct Interthread Communication On A Network On Chip Collecting and analyzing trace data while in a software debug mode through direct interthread communication (‘DITC’) on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network i... | 11/24/2011 |
| 20110276954 | SIMULTANEOUS COMPILER BINARY OPTIMIZATIONS The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors... | 11/10/2011 |
| 20110271259 | SYSTEMS AND METHODS FOR DEBUGGING APPLICATIONS USING DUAL CODE GENERATION Systems and methods provide a debugger that debugs code using two versions of code, an optimized and a debuggable version of object code for subroutines, methods or functions. The debugger causes the appropriate version of the code to be executed depending on whether de... | 11/03/2011 |
| 20110265069 | METHODS AND SYSTEMS FOR EXECUTION OF TENANT CODE IN AN ON-DEMAND SERVICE ENVIRONMENT INCLUDING UTILIZATION OF SHARED RESOURCES AND INLINE GOVERNOR LIMIT ENFORCEMENT A method for evaluating bytecode in an on-demand service environment. A request to compile source code is received in a multitenant database environment. One or more limit enforcement mechanisms is/are inserted into the source code to monitor utilization of one or more ... | 10/27/2011 |
| 20110246975 | CONTROL ARCHITECTURE AND PROCESS FOR PORTING APPLICATION SOFTWARE FOR EQUIPMENT ON BOARD AN AIRCRAFT TO A CONSUMER STANDARD COMPUTER HARDWARE UNIT The software unit arrangement method is a step of developing a standardized software-hardware abstraction software layer (6) in the software unit (1), the standardized software-hardware abstraction software layer (6) being made up of a library of pr... | 10/06/2011 |
| 20110219216 | Mechanism for Performing Instruction Scheduling based on Register Pressure Sensitivity A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software ... | 09/08/2011 |
| 20110219364 | Mechanism for Performing Register Allocation of Program Variables Based on Priority Spills and Assignments A mechanism for performing register allocation based on priority spills and assignments is disclosed. A method of embodiments of the invention includes repetitively detecting fat points during a compilation process of a software program running on a virtual machine of a... | 09/08/2011 |
| 20110202909 | TIER SPLITTING FOR OCCASIONALLY CONNECTED DISTRIBUTED APPLICATIONS Distributed programming is aided by tier splitting single-tier applications into multi-tier applications. Computations and persistent data are split across tiers to generate offlineable or occasionally connected distributed applications. More specifically, computations ... | 08/18/2011 |
| 20110191754 | SYSTEM USING A UNIQUE MARKER WITH EACH SOFTWARE CODE-BLOCK A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-bl... | 08/04/2011 |
| 20110191758 | Optimized Memory Allocator By Analyzing Runtime Statistics A computer readable storage medium including a set of instructions executable by a processor. The set of instructions operable to determine memory allocation parameters for a program executing using a standard memory allocation routine, create an optimized memory alloca... | 08/04/2011 |
| 20110191759 | Interactive Capacity Planning Techniques for performing capacity planning for applications running on a computational infrastructure are provided. The techniques include instrumenting an application under development to receive one or more performance metrics under a physical deployment plan, receiv... | 08/04/2011 |
| 20110185346 | AUTOMATED BUILDING AND RETARGETING OF ARCHITECTURE-DEPENDENT ASSETS Architecture-dependent assets are automatically built and retargeted. An asset originally built for one architecture is downloaded and automatically retargeted on another architecture. This automatically retargeting may be performed on demand, at runtime.... | 07/28/2011 |
| 20110179404 | SYSTEM AND METHOD FOR CODE AUTOMATION A system is provided for computer application code automation comprising a code automation computer server configured for presenting an electronic user interface for receiving user input for generating a Structured Query Language (SQL) query, the user input comprising a... | 07/21/2011 |
| 20110145802 | ACCELERATING UNBOUNDED MEMORY TRANSACTIONS USING NESTED CACHE RESIDENT TRANSACTIONS Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a s... | 06/16/2011 |
| 20110099535 | Encoding Switch on Ordered Universes with Binary Decision Diagrams Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a multi-way branch statement in a computer programming language. The multi-way branch statement may include a plurality of case labels each having a non-pri... | 04/28/2011 |
| 20110093661 | MULTIPROCESSOR SYSTEM WITH MIXED SOFTWARE HARDWARE CONTROLLED CACHE MANAGEMENT A multiprocessor system has a background memory and a plurality of processing elements (10), each comprising a processor core (100) and a cache circuit (102). The processor cores (100) execute programs of instructions and the cache circuits (... | 04/21/2011 |
| 20110078424 | OPTIMIZING PROGRAM CODE USING BRANCH ELIMINATION A method for optimizing program code is provided. The method comprises detecting a branch instruction comprising a condition expression, wherein the branch instruction, when executed by a processor, causes the processor to execute either a first set of instructions or a... | 03/31/2011 |
| 20110078671 | OPTIMIZATION OF META-TEMPLATE INSTANTIATIONS An illustrative embodiment provides a computer-implemented method for an alternate type system for optimizing the evaluation and use of meta-template instantiations. The computer-implemented method obtains a source code, instantiates an element of the source code to for... | 03/31/2011 |
| 20110010696 | DUPLICATE VIRTUAL FUNCTION TABLE REMOVAL One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first ob... | 01/13/2011 |
| 20110004869 | PROGRAM, APPARATUS, AND METHOD OF OPTIMIZING A JAVA OBJECT An apparatus, method and article of manufacture tangibly embodying computer readable instructions for optimizing a Java object on a target computer program. The apparatus includes: a storage unit for storing a value of the object and management information on the object... | 01/06/2011 |
| 20100275192 | Generating optimal instruction sequences for bitwise logical expressions A sequence generator generates a table of optimal instruction sequences for all bitwise expression having a specific number of variables. An index generator generates a bit-string index that corresponds to a particular bitwise expression. The bit-string is generated fro... | 10/28/2010 |
| 20100274663 | RESOURCE OPTIMIZATION A network, method and program for allocating viewable screen area resources amongst a plurality of competing portions of content in a network comprising a plurality of end-user terminals and one or more servers operatively coupled to the end-user terminals over the netw... | 10/28/2010 |
| 20100275193 | REDUCING MEMORY USAGE OF KERNEL MEMORY MANAGEMENT STRUCTURES One aspect of the present invention relates to techniques utilized within an operating system or a similar virtualization environment for reducing overhead of memory management data structures. Memory management data structures are used by operating systems to track the... | 10/28/2010 |
| 20100241892 | Energy Optimization Through Intentional Errors Technologies are described herein for intentionally allowing errors in a computational system to optimize energy consumption of the computational system. A cost-benefit analysis is performed to identify one or more allowable errors and one or more non-allowable errors i... | 09/23/2010 |
| 20100223605 | APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELIZING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline.... | 09/02/2010 |
| 20100205591 | PRESENTING ENERGY CONSUMPTION INFORMATION IN AN INTEGRATED DEVELOPMENT ENVIRONMENT TOOL Embodiments of the invention provide techniques for presenting energy consumption information in an IDE tool. In one embodiment, the IDE tool may be configured to determine energy requirements associated with specific elements of the source code, and to present graphica... | 08/12/2010 |
| 20100199270 | SYSTEM, METHOD, AND COMPUTER-PROGRAM PRODUCT FOR SCALABLE REGION-BASED REGISTER ALLOCATION IN COMPILERS A region-based register allocation system, method, and computer-program product not only provides a scalable framework across multiple applications, but also improves application runtime. They include a register pressure based model, to determine when using multiple reg... | 08/05/2010 |
