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| Application No. | Application Title | Issue Date |
| 20100306719 | Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods A layout of cells is generated to satisfy a netlist of an integrated circuit. Cell-level process compensation technique (PCT) processing is performed on a number of levels of one or more cells in the layout to generate a PCT processed version of the one more cells in th... | 12/02/2010 |
| 20100295606 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT SYSTEM, DESIGN SUPPORT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit design support system having a partial power control mechanism includes a partial power control simulation program configured to perform a partial power control simulation on the basis of a circuit description of the semiconductor inte... | 11/25/2010 |
| 20100290299 | SEMICONDUCTOR CHIP AND METHOD OF REPAIR DESIGN OF THE SAME A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of ... | 11/18/2010 |
| 20100283128 | Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a d... | 11/11/2010 |
| 20100276809 | T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the... | 11/04/2010 |
| 20100281443 | Change Point Finding Method and Apparatus A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HD... | 11/04/2010 |
| 20100281442 | TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-... | 11/04/2010 |
| 20100275172 | RULE CHECK SYSTEM, DESIGN RULE CHECK METHOD AND DESIGN RULE CHECK PROGRAM A design rule check system includes: a design rule check unit that performs a design rule checks on wiring information which indicates a wiring pattern of a net on the basis of a design rule which includes a constraint condition of a wiring pattern; and a screening proc... | 10/28/2010 |
| 20100269076 | TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM A test pattern generation apparatus includes an activation rate setting unit configured to set an activation rate of a cell, a test pattern generator configured to generate a test pattern based on the activation rate set by the activation rate setting unit, a supply vol... | 10/21/2010 |
| 20100269075 | METHOD AND SYSTEM FOR SELECTIVE STRESS ENABLEMENT IN SIMULATION MODELING A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defin... | 10/21/2010 |
| 20100269074 | Predictive Power Management Semiconductor Design Tool and Methods for Using Such Various embodiments of the present invention provide systems and methods for improved semiconductor design. For example, various embodiments of the present invention provide methods for semiconductor design that include receiving a semiconductor design with at least a f... | 10/21/2010 |
| 20100269073 | Proprietary circuit layout identification A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previo... | 10/21/2010 |
| 20100257493 | EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter co... | 10/07/2010 |
| 20100244132 | Methods for Normalizing Strain in Semiconductor Devices and Strain Normalized Semiconductor Devices A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistor... | 09/30/2010 |
| 20100243414 | Horizontal Micro-Electro-Mechanical-System Switch A first dielectric material layer and a second dielectric material layer are formed on a substrate. Three conductive portions are formed within the second dielectric material layer. An optional third dielectric material layer and an optional dielectric capping layer may... | 09/30/2010 |
| 20100246076 | Electrical Overstress Protection Circuit A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic ... | 09/30/2010 |
| 20100244934 | SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The sh... | 09/30/2010 |
| 20100242001 | Parameter Drift Prediction A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a r... | 09/23/2010 |
| 20100242002 | Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method A structure analysis apparatus (1) for analyzing structure of a complex material layer containing a plurality of members (2a, 2b) for modeling layout data on a complex material layer, includes: an area setting portion (21) for s... | 09/23/2010 |
| 20100237900 | Semiconductor integrated circuit including a power controllable region Provided is a semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit including a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power co... | 09/23/2010 |
| 20100242000 | USING LAYOUT ENUMERATION TO FACILITATE INTEGRATED CIRCUIT DEVELOPMENT A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining a... | 09/23/2010 |
| 20100230753 | LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having th... | 09/16/2010 |
| 20100229138 | Circuit design supporting apparatus and circuit design supporting method A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element sub... | 09/09/2010 |
| 20100229133 | Property-Based Classification In Electronic Design Automation One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified ... | 09/09/2010 |
| 20100229132 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequentia... | 09/09/2010 |
| 20100218153 | SUPPORTING PROGRAM, DESIGN SUPPORTING DEVICE AND DESIGN SUPPORTING METHOD A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corr... | 08/26/2010 |
| 20100218146 | SYNTHESIS USING MULTIPLE SYNTHESIS ENGINE CONFIGURATIONS Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or ... | 08/26/2010 |
| 20100218147 | CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING DEVICE, CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING METHOD AND STORAGE MEDIUM A design analyzing device includes a circuit specification description analyzing section configured to create structure data about an assertion description, a pass pattern creating section configured to create data about a plurality of pass patterns for which the assert... | 08/26/2010 |
| 20100205570 | Method For Reading Polygon Data Into An Integrated Circuit Router An approach is provided for converting a polygon described as an ordered list of perimeter points into a set of connected quadrilaterals suitable for use in an advanced integrated circuit router. Edges are constructed between the points of the polygon. Then, one or more... | 08/12/2010 |
| 20100205574 | SUPPORT APPARATUS AND METHOD A design support apparatus includes: a logical expression substitution unit to substitute a part of the logical expression, which includes a function expression of the design variables and a quantifier attached to the design variable, with a substitution variable; a qua... | 08/12/2010 |
| 20100199240 | Parallel Electronic Design Automation: Shared Simultaneous Editing A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the de... | 08/05/2010 |
| 20100199237 | TRANSFORMING VARIABLE DOMAINS FOR LINEAR CIRCUIT ANALYSIS Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain ... | 08/05/2010 |
| 20100199239 | SIMULATION METHOD AND SIMULATION PROGRAM There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first pro... | 08/05/2010 |
| 20100199238 | Systematic Method for Variable Layout Shrink A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percen... | 08/05/2010 |
| 20100187525 | IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULATION OF CAPACITANCE A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including th... | 07/29/2010 |
| 20100192112 | DIAGNOSTIC APPARATUS FOR SEMICONDUCTOR DEVICE, DIAGNOSTIC METHOD FOR SEMICONDUCTOR DEVICE, AND MEDIUM STORING DIAGNOSTIC PROGRAM FOR SEMICONDUCTOR DEVICE A diagnostic apparatus for semiconductor device includes a fault cell list generation unit configured to extract fault cell candidates corresponding to light emission position information, to generate a fault cell list on the basis of the light emission image informatio... | 07/29/2010 |
| 20100181621 | SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD... | 07/22/2010 |
| 20100164013 | RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly o... | 07/01/2010 |
| 20100169852 | SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS A system and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits. A method for detecting invalid winding path in a layout design. The method includes the step of obtaining a first winding path... | 07/01/2010 |
| 20100169855 | METHOD AND SYSTEM DETECTING METAL LINE FAILURE In a method of detecting metal line failures for a full-chip, a first net-list is converted to a second net-list. The first net-list includes first information related to elements and metal lines, and the second net-list includes second information susceptible to direct... | 07/01/2010 |
