An enclosure for small animals which is wearable on the front or back of an animate being.
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| Application No. | Application Title | Issue Date |
| 20100299646 | UNIFORMITY FOR SEMICONDUCTOR PATTERNING OPERATIONS Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a l... | 11/25/2010 |
| 20100269084 | Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography Kernels that model characteristics of the etching portion of an optical lithographic model are provided. In various implementations, a visibility density kernel is provided. The visibility density kernel approximates the area of the simulated substrate that is “visibl... | 10/21/2010 |
| 20100218160 | METHOD AND APPARATUS FOR DETERMINING A PROCESS MODEL THAT MODELS THE IMPACT OF A CAR/PEB ON THE RESIST PROFILE An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine... | 08/26/2010 |
| 20100186000 | APPARATUS AND METHOD FOR SEGMENTING EDGES FOR OPTICAL PROXIMITY CORRECTION An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.... | 07/22/2010 |
| 20100185999 | SHORT PATH CUSTOMIZED MASK CORRECTION Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; catego... | 07/22/2010 |
| 20100175041 | ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an op... | 07/08/2010 |
| 20100167184 | LITHOGRAPHIC PROCESSING METHOD, AND DEVICE MANUFACTURED THEREBY A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and ... | 07/01/2010 |
| 20100167537 | PARTITIONING FEATURES OF A SINGLE IC LAYER ONTO MULTIPLE PHOTOLITHOGRAPHIC MASKS One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from th... | 07/01/2010 |
| 20100127331 | ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer... | 05/27/2010 |
| 20100035367 | FILM THICKNESS PREDICTION METHOD, LAYOUT DESIGN METHOD, MASK PATTERN DESIGN METHOD OF EXPOSURE MASK, AND FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT A film thickness prediction method of predicting a film thickness of a second processed layer after planarization includes the steps of: creating first to third actual measurement databases; obtaining a reference film thickness of a second processed layer formed on a re... | 02/11/2010 |
| 20090271759 | CONTRAST-BASED RESOLUTION ENHANCEMENT FOR PHOTOLITHOGRAPHIC PROCESSING A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments hav... | 10/29/2009 |
| 20090204936 | Method of Performing Proximity Correction A method of performing proximity correction of a mask layout is used during the generation of a masking structure for performing a processing step. The masking structure includes at least one opening that is delimited by a sidewall and that exposes an area that is to be... | 08/13/2009 |
| 20090199151 | ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a pl... | 08/06/2009 |
| 20090193386 | SEMICONDUCTOR CELL FOR PHOTOMASK DATA VERIFICATION AND SEMICONDUCTOR CHIP A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout da... | 07/30/2009 |
| 20090178018 | PRE-BIAS OPTICAL PROXIMITY CORRECTION A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.... | 07/09/2009 |
| 20090146322 | METHOD OF ELIMINATING A LITHOGRAPHY OPERATION Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on t... | 06/11/2009 |
| 20090119635 | MASK PATTERN CORRECTION METHOD FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Mask data is generated from a design layout by executing a mask data process including optical proximity correction. A pattern is formed on the major surface of a test semiconductor substrate by using a mask prepared from the mask data. The dimensional difference betwee... | 05/07/2009 |
| 20090070732 | Fracture Shot Count Reduction Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that... | 03/12/2009 |
| 20090044167 | PROCESS-MODEL GENERATION METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN CORRECTION METHOD A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different mo... | 02/12/2009 |
| 20090037868 | AREA BASED OPTICAL PROXIMITY CORRECTION IN RASTER SCAN PRINTING Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.... | 02/05/2009 |
| 20090013304 | Physical-Resist Model Using Fast Sweeping A method for determining a surface in a material is described. During this method, arrival times of a wavefront at a first depth in the material are calculated using an Eikonal equation. Note that the first depth is proximate to an outer surface of the material. Next, a... | 01/08/2009 |
| 20080315365 | Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the... | 12/25/2008 |
| 20080320434 | PHOTOMASK MANAGEMENT METHOD AND PHOTOMASK WASH LIMIT GENERATING METHOD A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern pr... | 12/25/2008 |
| 20080288912 | METHOD OF INSPECTING MASK USING AERIAL IMAGE INSPECTION APPARATUS A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an insp... | 11/20/2008 |
| 20080282218 | Method for Designing Mask A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offs... | 11/13/2008 |
| 20080276215 | Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention p... | 11/06/2008 |
| 20080244504 | Method and apparatus for determining mask layouts for a multiple patterning process One embodiment provides a method for determining mask layouts. During operation, the system can receive a design intent. Next, the system can determine a set of critical edges in the design layout, and select a first edge and a second edge. The system can then determine... | 10/02/2008 |
| 20080209386 | METHOD FOR PREDICTING RESIST PATTERN SHAPE, COMPUTER READABLE MEDIUM STORING PROGRAM FOR PREDICTING RESIST PATTERN SHAPE, AND COMPUTER FOR PREDICTING RESIST PATTERN SHAPE The contour shape of an aerial image formed on a resist by projecting a test pattern onto the resist via a projection optical system is computed. The shape of a resist pattern formed by the exposure using the test pattern and the development process is measured. A corre... | 08/28/2008 |
| 20080185735 | Dynamic pad size to reduce solder fatigue A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the mi... | 08/07/2008 |
| 20080174756 | Source optimization for image fidelity and throughput A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed patt... | 07/24/2008 |
| 20080178142 | Hotspot detection method for design and validation of layout for semiconductor device A hotspot detection method for detecting a hotspot in a layout for a semiconductor device, includes: dividing a target analysis area into a grid based on layout data about the semiconductor device; and determining whether the grid falls into a hotspot or not, based on t... | 07/24/2008 |
| 20080168417 | Integrated assist features for epitaxial growth bulk tiles with compensation A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307 | 07/10/2008 |
| 20080168418 | Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307 | 07/10/2008 |
| 20080138720 | METHOD OF ARRANGING MASK PATTERNS AND APPARATUS USING THE METHOD In positioning assist features on a photomask pattern to improve the image quality of the main features, the method includes deriving an h-function in a first process which represents a contribution of an assist feature with respect to image intensity at a main feature.... | 06/12/2008 |
| 20080136043 | Multilayer Wiring Structure, Semiconductor Device, Pattern Transfer Mask and Method for Manufacturing Multilayer Wiring Structure A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region... | 06/12/2008 |
| 20080134129 | DESIGN RULE CHECKING FOR ALTERNATING PHASE SHIFT LITHOGRAPHY In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating a first set of polygons to define a trim photomask, generating a second set of polygons to define a phase photomask, and determining which edges of th... | 06/05/2008 |
| 20080116398 | Method and system for proximity effect and dose correction for a particle beam writing device A method of particle beam lithography includes selecting at least two cell patterns from a stencil, correcting proximity effect by dose control and by pattern modification for the at least two cell patterns, and writing the at least cell two patterns by one shot of the ... | 05/22/2008 |
| 20080092106 | Method for performing pattern pitch-split decomposition utilizing anchoring features A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of: (a) determining a minimum critical dimension and pitch associated with a process to be utilized to image the multiple pattern... | 04/17/2008 |
| 20080077907 | Neural network-based system and methods for performing optical proximity correction An optical proximity corrected mask design is generated from a given a target mask design by processing the target mask design through a feature trained neural network, configured to perform an optical proximity correction of geometric features, to obtain a representati... | 03/27/2008 |
| 20080059939 | PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon ... | 03/06/2008 |