Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20100281448 | LOW-POWER FPGA CIRCUITS AND METHODS Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous por... | 11/04/2010 |
| 20100248432 | METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one... | 09/30/2010 |
| 20100231263 | Logic Circuit and Method of Logic Circuit Design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for conn... | 09/16/2010 |
| 20100213977 | USERS REGISTERS IMPLEMENTED WITH ROUTING CIRCUITS IN A CONFIGURABLE IC Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circ... | 08/26/2010 |
| 20100213974 | Method and apparatus for camouflaging a printed circuit board A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of ... | 08/26/2010 |
| 20100218158 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternat... | 08/26/2010 |
| 20100207659 | FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up... | 08/19/2010 |
| 20100182042 | Circuits and Methods for Programmable Transistor Array A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor ... | 07/22/2010 |
| 20100180246 | RANDOM GENERATION OF PLD CONFIGURATIONS TO COMPENSATE FOR DELAY VARIABILITY A method of generating a user circuit implementation for programming a PLD comprising generating a set of user circuit implementation configuration candidates, measuring one or more characteristics of the PLD in a measurement phase and selecting a user circuit implement... | 07/15/2010 |
| 20100169856 | TRANSPARENT TEST METHOD AND SCAN FLIP-FLOP Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by dais... | 07/01/2010 |
| 20100138804 | Methods and Apparatuses for Automated Circuit Design Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodimen... | 06/03/2010 |
| 20100100864 | FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output nod... | 04/22/2010 |
| 20100100857 | GENERIC NON-VOLATILE SERVICE LAYER Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. Th... | 04/22/2010 |
| 20100066407 | Operational Time Extension Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits.... | 03/18/2010 |
| 20100070942 | Automated Metal Pattern Generation for Integrated Circuits An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs;... | 03/18/2010 |
| 20100058274 | FLEXIBLE HARDWARE UPGRADE MECHANISM FOR DATA COMMUNICATIONS EQUIPMENT Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial reconfiguration may enable alteration of a clock frequency without affecting operation ... | 03/04/2010 |
| 20100031222 | BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions... | 02/04/2010 |
| 20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in s... | 02/04/2010 |
| 20100017774 | METHOD AND SYSTEM FOR MOUNTING CIRCUIT DESIGN ON RECONFIGURABLE DEVICE There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system (30) includes a database (31) for storing hardware information (89) inc... | 01/21/2010 |
| 20100017775 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chi... | 01/21/2010 |
| 20100008155 | Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configura... | 01/14/2010 |
| 20100005431 | CONVERTING A SYNCHRONOUS CIRCUIT DESIGN INTO AN ASYNCHRONOUS DESIGN Methods and systems for converting synchronous circuit designs to asynchronous circuit designs are described. A method may include converting a synchronous circuit design to an asynchronous dataflow design. Functional characteristics of the synchronous circuit design ma... | 01/07/2010 |
| 20090327987 | Timing operations in an IC with configurable circuits Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning t... | 12/31/2009 |
| 20090319975 | Method and system for the modular design and layout of integrated circuits An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and ... | 12/24/2009 |
| 20090300571 | METHODS AND SYSTEMS FOR FPGA REWIRING There are disclosed a method and system for FPGA rewiring of a circuit. The method comprises: mapping the circuit into a first circuit, the first circuit being logically represented with a plurality of Look-Up Tables; rewiring the first circuit to obtain a second circui... | 12/03/2009 |
| 20090293035 | INCREASED EFFECTIVE FLIP-FLOP DENSITY IN A STRUCTURED ASIC An H-tree is formed in a conducting layer over the base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential ... | 11/26/2009 |
| 20090289696 | Apparatus and Methods for Adjusting Performance of Integrated Circuits A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within... | 11/26/2009 |
| 20090288057 | System and Method for Ordering the Selection of Integrated Circuit Chips A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to receive and store an electronic wafer map that contains coordinates and charac... | 11/19/2009 |
| 20090271747 | LOGIC CIRCUIT DESIGNING DEVICE, LOGIC CIRCUIT DESIGNING METHOD AND LOGIC CIRCUIT DESIGNING PROGRAM FOR ASYNCHRONOUS LOGIC CIRCUIT A logic circuit designing device for designing an asynchronous logic circuit which satisfies characteristic constraints of a state holding element represented by a latch or a flip-flop is provided. A signal transition series which generates a control signal pulse of the... | 10/29/2009 |
| 20090249276 | METHODS AND SYSTEMS FOR FPGA REWIRING AND ROUTING IN EDA DESIGNS Disclosed are a method and a system for improving FPGA routings of a circuit. The method comprises: identifying candidate alternative wires for a target wire to be replaced in the circuit according to a first preset rule; selecting a first set of alternative wires from ... | 10/01/2009 |
| 20090241083 | ROUTER-AIDED POST-PLACEMENT-AND-ROUTING-RETIMING A method of minimising the longest delay path between two logic elements of a circuit placed on a reconfigurable device, each logic element being associated with a register and the reconfigurable device including logic elements and associated registers which are program... | 09/24/2009 |
| 20090237113 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and s... | 09/24/2009 |
| 20090235222 | CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist (110), mapping logic gates of the netlist to functionally equiv... | 09/17/2009 |
| 20090204935 | Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. ... | 08/13/2009 |
| 20090193384 | SHIFT-ENABLED RECONFIGURABLE DEVICE A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array contains partially or fully populated matrices of switches, where each such matr... | 07/30/2009 |
| 20090178017 | SYSTEM AND METHOD FOR I/O SYNTHESIS AND FOR ASSIGNING I/O TO PROGRAMMABLE DEVICES A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, an... | 07/09/2009 |
| 20090160482 | Formation of a hybrid integrated circuit device Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the ... | 06/25/2009 |
| 20090101940 | DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be ... | 04/23/2009 |
| 20090070727 | Three dimensional integrated circuits and methods of fabrication Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs.... | 03/12/2009 |
| 20090070728 | IP cores in reconfigurable three dimensional integrated circuits The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of... | 03/12/2009 |
