Class 716/1 - CIRCUIT DESIGN

Subclass of Class 716 - Data processing: design and analysis of circuit or semiconductor mask
Definition: Subject matter comprising means or steps for sketching
No. of applications: 386
Last issue date: 12/02/2010

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Application No.	Application Title	Issue Date
20100301922	FIELD EFFECT TRANSISTOR WITH INTEGRATED GATE CONTROL AND RADIO FREQUENCY SWITCH A field effect transistor (FET) including a monolithically integrated gate control circuit element can be included in, for example, a radio frequency switch circuit. For example, the FET can be included as a series and/or shunt FET of a radio frequency coplanar waveguid...	12/02/2010
20100265011	CIRCUIT STRUCTURE AND DESIGN STRUCTURE FOR AN OPTIONALLY SWITCHABLE ON-CHIP SLOW WAVE TRANSMISSION LINE BAND-STOP FILTER AND A METHOD OF MANUFACTURE The present invention generally relates to a circuit structure, design structure and method of manufacturing a circuit, and more specifically to a circuit structure and design structure for an on-chip slow wave transmission line band-stop filter and a method of manufact...	10/21/2010
20100257492	ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are...	10/07/2010
20100244132	Methods for Normalizing Strain in Semiconductor Devices and Strain Normalized Semiconductor Devices A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistor...	09/30/2010
20100244179	STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure....	09/30/2010
20100237464	Chip Inductor With Frequency Dependent Inductance A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal...	09/23/2010
20100237468	ON-CHIP CAPACITORS WITH A VARIABLE CAPACITANCE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polariti...	09/23/2010
20100237324	Semiconductor Switching Circuit Employing Quantum Dot Structures A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at lea...	09/23/2010
20100230729	PIXEL SENSOR CELL INCLUDING LIGHT SHIELD CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumina...	09/16/2010
20100229133	Property-Based Classification In Electronic Design Automation One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified ...	09/09/2010
20100213547	SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickn...	08/26/2010
20100201465	APPARATUS AND METHOD FOR ELECTROMAGNETIC MODE SUPPRESSION IN MICROWAVE AND MILLIMETERWAVE PACKAGES A parallel plate waveguide structure may be configured to suppress spurious propagating modes by including a lossy frequency selective surface (FSS). The electromagnetic material properties of individual layers disposed between the conductive plates of the waveguide may...	08/12/2010
20100201440	SOI RADIO FREQUENCY SWITCH WITH REDUCED SIGNAL DISTORTION A doped semiconductor region having a same conductivity type as a bottom semiconductor layer is formed underneath a buried insulator layer in a bottom semiconductor layer of a semiconductor-on-insulator (SOI) substrate. At least one conductive via structure is formed, w...	08/12/2010
20100199244	Formal Verification Of Clock Domain Crossings Methods and apparatus for performing automated formal clock domain crossing verification on a device are detailed. In various implementations of the invention, a device may be analyzed, wherein the clock domain crossing boundaries are identified. Subsequently, a formal ...	08/05/2010
20100199233	Uniquely Marking Products And Product Design Data Methods and apparatuses for marking the product of an unauthorized use of a process are provided. For example, various implementations of the invention may cause a product to be marked when it is produced by the unauthorized use of a process. With some implementations o...	08/05/2010
20100194459	CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipe...	08/05/2010
20100187525	IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULATION OF CAPACITANCE A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including th...	07/29/2010
20100176848	INPUT/OUTPUT BUFFER CIRCUIT A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an ...	07/15/2010
20100173449	METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer ...	07/08/2010
20100174923	Regulating Power Consumption Methods, systems, and design structures for providing power-regulated multi-core processing. The method includes determining a configuration of processing cores for optimal power consumption. The configuration of processing cores for optimal power consumption comprises ...	07/08/2010
20100156466	Implementing Power Savings in HSS Clock-Gating Circuit A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit i...	06/24/2010
20100149701	ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy thro...	06/17/2010
20100148836	Contention-Free Level Converting Flip-Flops for Low-Swing Clocking The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swi...	06/17/2010
20100127801	LOW PASS FILTER WITH EMBEDDED RESONATOR An embedded resonator sharpens the frequency characteristics of a coaxial low pass filter. The resonator introduces finite transmission zeros to the response of the low pass filter, thereby suppressing spurious modes occurring just above the operating frequency. Two par...	05/27/2010
20100131915	Method, device, and program for predicting a manufacturing defect part of a semiconductor device Provided is a method of predicting a manufacturing defect part of a semiconductor device, which results from optical pattern displacement in an exposure process. The prediction method includes: performing repetitive processing a plurality of times, the repetitive proces...	05/27/2010
20100131934	SYSTEM AND METHOD FOR TRANSLATING HIGH-LEVEL PROGRAMMING LANGUAGE CODE INTO HARDWARE DESCRIPTION LANGUAGE CODE The present invention is directed to a method and system for translating a high-level language (HLL) code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL which requires no modification in the original HLL source code, while supporting a...	05/27/2010
20100114761	AREA TRIM SERVICE BUSINESS METHOD A method for manufacturing integrated circuits (“ICs”) is disclosed. The method pertains to providing third-party technology in the form of an IC design library to foundry customers for designing IC products using alternate rule sets. Aggressive rules pertaining to ...	05/06/2010
20100115478	METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the t...	05/06/2010
20100115474	NON-CONTACT POWER TRANSMISSION APPARATUS AND METHOD FOR DESIGNING NON-CONTACT POWER TRANSMISSION APPARATUS A non-contact power transmission apparatus having a resonance system is disclosed. The resonance system includes a primary coil to which an alternating-current voltage from an alternating-current source is applied, a primary-side resonance coil, a secondary-side resonan...	05/06/2010
20100107130	1XN BLOCK BUILDER FOR 1XN VLSI DESIGN Embodiments that generate 1×N building block representations for an IC design via a GUI of a 1×N block builder are disclosed. Some embodiments enable, via a GUI, selection of a logical function for a 1×N building block. The embodiments also comprise enabling selectio...	04/29/2010
20100097511	HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The d...	04/22/2010
20100090722	High speed integrated circuit A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is...	04/15/2010
20100090760	Low-distortion voltage variable capacitor assemblies An embodiment of the present invention provides an apparatus, comprising a first half cell comprising a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which one or more of the two or more VVCs with the same bias voltage orientat...	04/15/2010
20100095252	CHANNEL LENGTH SCALING FOR FOOTPRINT COMPATIBLE DIGITAL LIBRARY CELL DESIGN Effective GDS-based channel length scaling. A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm...	04/15/2010
20100083193	DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit ...	04/01/2010
20100070942	Automated Metal Pattern Generation for Integrated Circuits An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs;...	03/18/2010
20100058258	Method of Estimating a Leakage Current in a Semiconductor Device In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents i...	03/04/2010
20100058278	METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS OF MULTI-CHANNEL CIRCUITS Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing...	03/04/2010
20100050135	VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF GOOD CHIP DIES HAVING MEMORIES PER WAFER A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum numb...	02/25/2010
20100038728	FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the c...	02/18/2010

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Class 716/1 - CIRCUIT DESIGN