A haircutting appliance comprises an enclosed housing having a hollow handle connecting the housing to a vacuum source to carry away cut hairs from a subject's head.
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| Application No. | Application Title | Issue Date |
| 20120042229 | MULTI-STANDARD VITERBI PROCESSOR Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-... | 02/16/2012 |
| 20120036416 | LIST VITERBI DECODING OF TAIL BITING CONVOLUTIONAL CODES A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a... | 02/09/2012 |
| 20110307767 | METHOD AND APPARATUS FOR SIGNAL-TO-NOISE RATIO ESTIMATION IN CONVOLUTIONAL CODES (VITERBI) DECODER A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths ma... | 12/15/2011 |
| 20110289376 | ENHANCED MULTILEVEL MEMORY Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.... | 11/24/2011 |
| 20110283170 | Viterbi Decoder and Writing and Reading Method A Viterbi decoder includes a survival memory unit, for storing a plurality of survivor metric into a writing column of a writing bank of a plurality of banks in alternating intervals of a clock according to a writing bank order and a writing column order, and a trace ba... | 11/17/2011 |
| 20110264988 | CONVOLUTIONAL CODE FOR USE IN A COMMUNICATION SYSTEM In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver compri... | 10/27/2011 |
| 20110264983 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND SIGNAL REPRODUCING APPARATUS According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according t... | 10/27/2011 |
| 20110231741 | SYSTEM AND METHOD FOR VITERBI DECODING USING APPLICATION SPECIFIC EXTENSIONS A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.... | 09/22/2011 |
| 20110167323 | Error-Correcting Apparatus and Method Thereof The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according ... | 07/07/2011 |
| 20110161787 | POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received ... | 06/30/2011 |
| 20110138260 | LDPC coding process with incremental redundancy The invention relates to a coding method with incremental redundancy in which it is determined (620) whether to carry out the coding of a sequence of information symbols using a first code (C), of the LDPC type, defined by a first check matrix, H, or rather using... | 06/09/2011 |
| 20110138259 | High Performance Digital Signal Processing In Software Radios An extensive use of look-up table (LUT) and single instruction multiple data (SIMD) in different algorithms in a software-defined radio (SDR) system is described. In particular, the LUT is used during spreading modulation, mapping and spreading, scrambling, de-scramblin... | 06/09/2011 |
| 20110129044 | APPARATUS AND METHOD FOR IMPROVING ERROR CORRECTION CAPABILITY USING STUFFING BYTE A decoding circuit and method for improving error correction capability using a stuffing byte, in which in the decoding method, an input data packet is decoded. When it is determined that error correction is impossible based on a decoding result, a stuffing byte section... | 06/02/2011 |
| 20110083063 | Continuous Parallel Viterbi Decoder A continuous parallel Viterbi decoder comprises input means for computing Trellis paths from an input bitstream encoded with a convolutional code; output means for backtracking the Trellis paths to generate an output signal; a shared memory for storing said Trellis path... | 04/07/2011 |
| 20110075287 | System and method for map detector for symbol based error correction codes A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder ... | 03/31/2011 |
| 20110060972 | DECODING METHOD FOR TAIL-BITING CONVOLUTIONAL CODES USING A SEARCH DEPTH VITERBI ALGORITHM A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as in... | 03/10/2011 |
| 20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits incl... | 02/03/2011 |
| 20110004806 | DATA RECEIVING CIRCUIT AND DATA PROCESSING METHOD A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-... | 01/06/2011 |
| 20100325525 | SOFT OUTPUT VITERBI DECODER ARCHITECTURE A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reli... | 12/23/2010 |
| 20100313103 | Receiver Equipped with a Trellis Viterbi Decoder A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received including a series of symbols, is provided. The receiver comprises a programmable logic circuit that includes a source memory A and a destination memor... | 12/09/2010 |
| 20100299583 | OPTIMIZED VITERBI DECODER AND GNSS RECEIVER A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design ... | 11/25/2010 |
| 20100287451 | Incremental generation of polynomials for decoding reed-solomon codes An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern i... | 11/11/2010 |
| 20100281334 | SYSTEMS AND METHODS FOR COMMUNICATIONS Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether app... | 11/04/2010 |
| 20100274218 | COMMUNICATIONS FOR MEDICINAL FLUID DELIVERY SYSTEM Disclosed are methods, devices, systems and computer program products for communicating between at least one unit of a therapeutic fluid dispensing device and at least another unit of the dispensing device. The method includes performing a determination whether a first ... | 10/28/2010 |
| 20100269026 | ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was p... | 10/21/2010 |
| 20100262896 | Signal mapper for reducing error coefficient An improved mapping policy, signal mapper, transmitter, receiver, and communication system are introduced. The improved signal mapping policy alternates between standard and inverted bit mapping functions at selected phase states to reduce the error coefficient of MSK a... | 10/14/2010 |
| 20100257435 | METHOD OF PROCESSING TRAFFIC INFORMATION AND DIGITAL BROADCAST SYSTEM A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic infor... | 10/07/2010 |
| 20100229076 | Decoding Apparatus and Decoding Method Disclosed herein is a decoding apparatus including: with N and x each being a positive integer and k being a positive integer being equal to or greater than 1, a shift register of k stages configured to accumulate path select information for k inputs that is information... | 09/09/2010 |
| 20100223537 | Method and System for Decoding Video, Voice, and Speech Data Using Redundancy A method and system for decoding video, voice, and/or speech data using redundancy and physical constraints are presented. Video, voice, and/or speech bit sequences may be decoded in a multilayer process based on a decoding algorithm and at least one physical constraint... | 09/02/2010 |
| 20100211858 | Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific proces... | 08/19/2010 |
| 20100185923 | DECODING OF RECURSIVE CONVOLUTIONAL CODES BY MEANS OF A DECODER FOR NON-RECURSIVE CONVOLUTIONAL CODES Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder is used to at least partially perform the decoding of a recur... | 07/22/2010 |
| 20100185925 | Differential Locally Updating Viterbi Decoder The present invention relates to differential, locally updating Viterbi decoder characterized in that it contains connection management block (802, 810, 812) which enables decoding a bit per cycle by trellis diagram uniting (810) and distributing procedure... | 07/22/2010 |
| 20100169749 | METHOD AND APPARATUS FOR CONCATENATED CONVOLUTIONAL ENCODING AND INTERLEAVING A method and apparatus encode a source data stream via convolutional encoding or selected encoding scheme. Plural encoded data streams are interleaved and transmitted on a transmission channel. Data groups generated via convolutional or selected encoding are interleaved... | 07/01/2010 |
| 20100169746 | LOW-COMPLEXITY SOFT-DECISION DECODING OF ERROR-CORRECTION CODES A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identif... | 07/01/2010 |
| 20100070834 | Soft output viterbi detector with error event output Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associat... | 03/18/2010 |
| 20100070835 | Method and Apparatus for Error Compensation Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to com... | 03/18/2010 |
| 20100064201 | APPARATUS AND METHOD OF GENERATING REFERENCE LEVEL OF VITERBI DECODER An apparatus of generating the optimum reference level of a Viterbi decoder for an input signal includes: a first reference level detection unit detecting a first reference level using a delayed input signal from the Viterbi decoder and an output signal of the Viterbi d... | 03/11/2010 |
| 20100058152 | DECODING APPARATUS AND METHOD A-decoding-apparatus includes first-equalization-unit configured to obtain an-equalized-bit-string subjected to hard-decision by equalizing the-input-signal, and to obtain reliability-value-data as soft-decision which is indicating reliability of the-hard-decision with ... | 03/04/2010 |
| 20100042877 | Systems and Methods for Media Defect Detection Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the... | 02/18/2010 |
| 20100034325 | LOW-POWER PREDECODING BASED VITERBI DECODING In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logi... | 02/11/2010 |