Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Application No. | Application Title | Issue Date |
| 20120042228 | BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take p... | 02/16/2012 |
| 20120030535 | Distributed Block Coding (DBC) Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the s... | 02/02/2012 |
| 20120011420 | CHANNEL EQUALIZER AND METHOD OF PROCESSING TELEVISION SIGNAL IN DTV SYSTEM A channel equalizer includes a channel estimator, a coefficient calculator, a multiplier, and an error remover. The channel estimator estimates a channel impulse response (CIR) of input data in which a known data sequence is periodically inserted. The coefficient calcul... | 01/12/2012 |
| 20120011419 | TRANSMISSION SYSTEM, METHOD AND PROGRAM A transmitting apparatus generates and transmits 3t+1 or more number of codewords for a message and multiple faulty encoded message identifying data, wherein the information regarding the message may not be obtained from t or less number of encoded messages and the mess... | 01/12/2012 |
| 20110320918 | ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devic... | 12/29/2011 |
| 20110307757 | SYSTEMS AND METHODS FOR ERROR CORRECTION Systems, methods, and an article of manufacture for decoding a broadcast signal are shown and described. In particular, aspects of the Reed-Solomon decoding algorithm are improved to thereby reduce the amount of processing time required to execute the Reed-Solomon decod... | 12/15/2011 |
| 20110302473 | ERROR CORRECTION CODING Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may t... | 12/08/2011 |
| 20110302475 | Advanced Bitwise Operations and Apparatus in a Multi-Level System with Nonvolatile Memory A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read oper... | 12/08/2011 |
| 20110283168 | Method of Handling Packet Loss Using Error-Correcting Codes and Block Rearrangement A method of handling packet loss uses errorcorrecting codes and block rearrangement. This method divides the original data stream into data blocks, then codes the blocks by errorcorrecting codes. After coding the blocks, rearranges the coding blocks for spreading origin... | 11/17/2011 |
| 20110267209 | TRELLIS ENCODER AND TRELLIS ENCODING DEVICE HAVING THE SAME A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensat... | 11/03/2011 |
| 20110258520 | LOCATING AND CORRECTING CORRUPT DATA OR SYNDROME BLOCKS Disclosed is a method and system of determining a data block of a RAID level 6 stripe that has corrupted or incorrect data. For each data block of the stripe, a reconstructed data block is created using the other data blocks and the P syndrome data block. The reconstruc... | 10/20/2011 |
| 20110252293 | Concatenated Coding Architecture for G.hnem PHY Embodiments provide a method for determining the number of parity bytes that are added by a Reed-Solomon encoder. The number of parity bytes are equivalent to the error correcting capability of the Reed-Solomon code. The number of parity bytes is based on the payload le... | 10/13/2011 |
| 20110239085 | ECC WITH OUT OF ORDER COMPLETION Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC deco... | 09/29/2011 |
| 20110214036 | DIGITAL TELEVISION TRANSMITTER/RECEIVER AND METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER/RECEIVER A digital television (DTV) transmitter/receiver and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expa... | 09/01/2011 |
| 20110214038 | Methods and Systems for Rapid Error Correction of Reed-Solomon Codes An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction... | 09/01/2011 |
| 20110191652 | MEMORY READ-CHANNEL WITH SELECTIVE TRANSMISSION OF ERROR CORRECTION DATA A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, erro... | 08/04/2011 |
| 20110191657 | Systems for High-Speed Backplane Applications Using FEC Encoding In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Eth... | 08/04/2011 |
| 20110185266 | METHOD OF DECODING A PATTERN-ENCODED COORDINATE A method of decoding a coding pattern disposed on or in a substrate. The method comprises the steps of: (a) operatively positioning an optical reader relative to a surface of the substrate; (b) capturing an image of a portion of the coding pattern, the coding pattern co... | 07/28/2011 |
| 20110154164 | TRANSMITTER AND RECEIVER FOR TERRESTRIAL DIGITAL MULTIMEDIA BROADCASTING Provided is a terrestrial digital broadcasting transmitter. The terrestrial digital broadcasting transmitter may include a Reed-Solomon (RS) encoder to RS-encode an inputted broadcast signal, a forward error correction (FEC) encoder to channel-encode an inputted additio... | 06/23/2011 |
| 20110154160 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the E... | 06/23/2011 |
| 20110145678 | DATA LINE STORAGE AND TRANSMISSION UTILIZING BOTH ERROR CORRECTING CODE AND SYNCHRONIZATION INFORMATION Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32... | 06/16/2011 |
| 20110138256 | Distributed Block Coding (DBC) Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the s... | 06/09/2011 |
| 20110119560 | Flash Memory Device Error Correction Code Controllers and Related Methods and Memory Systems An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correctio... | 05/19/2011 |
| 20110093758 | Multi-Hop Network Having Increased Reliability The present disclosure is directed to networks having increased reliability and associated methods. In one aspect, a method for increasing reliability of a multi-hop network can include generating an erasure correction packet from a data packet using an encoder system, ... | 04/21/2011 |
| 20110083051 | INTERLEAVED CORRECTION CODE TRANSMISSION An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the ... | 04/07/2011 |
| 20110078543 | PARALLEL INVERSIONLESS ERROR AND ERASURE PROCESSING A complementary error evaluator polynomial is generated by obtaining a syndrome polynomial and one or more erasure locations. The syndrome polynomial and the erasure locations are associated with Reed-Solomon encoded information. A complementary error evaluator polynomi... | 03/31/2011 |
| 20110060968 | Systems and Methods for Implementing Error Correction in Relation to a Flash Memory Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to ... | 03/10/2011 |
| 20110035648 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packe... | 02/10/2011 |
| 20110029844 | RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of... | 02/03/2011 |
| 20110004812 | CODER-DECODER AND METHOD FOR ENCODING AND DECODING AN ERROR CORRECTION CODE The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first ge... | 01/06/2011 |
| 20100332951 | METHOD FOR PERFORMING COPY BACK OPERATIONS AND FLASH STORAGE DEVICE The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC ... | 12/30/2010 |
| 20100332956 | POLYNOMIAL DIVISION Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divis... | 12/30/2010 |
| 20100318877 | ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding sc... | 12/16/2010 |
| 20100306618 | TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCASTING SIGNAL IN TRANSMITTING/RECEIVING SYSTEM A transmitting system, a receiving system, and a method of processing broadcast signals are disclosed. Herein, the transmitting system includes an RS frame encoder, a block processor, a group formatter, and a trellis encoding module. The RS frame encoder performs error ... | 12/02/2010 |
| 20100306621 | ENCODING AND DECODING DATA The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operat... | 12/02/2010 |
| 20100306628 | COMPUTER READABLE MEDIUM WITH INSTRUCTIONS FOR RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of... | 12/02/2010 |
| 20100306626 | METHODS OF DATA HANDLING Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data i... | 12/02/2010 |
| 20100299580 | BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to calculate a plurality of preliminary syndromes from a plurality of received symbols. The second circuit may be configured to calculat... | 11/25/2010 |
| 20100299578 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA A transmitting apparatus in a transport network performs forward error correcting encoding for each virtual lane set as a multiple of the transmission channels, to generate virtual frames including independent parity bytes for each virtual lane. The generated virtual fr... | 11/25/2010 |
| 20100287444 | DIGITAL BROADCASTING SYSTEM AND DATA PROCESSING METHOD A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast ... | 11/11/2010 |
