Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Application No. | Application Title | Issue Date |
| 20120131417 | CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is... | 05/24/2012 |
| 20120131419 | MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data ... | 05/24/2012 |
| 20120131418 | MEMORY DEVICE According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of ... | 05/24/2012 |
| 20120110416 | DATA STORAGE APPARATUS WITH ENCODER AND DECODER According to one embodiment, an encoder/decoder apparatus includes an encoder module, a decoder module, and a transposing module. The encoder module is configured to generate a Hamming code from the input data, in accordance with a check matrix having a specific regular... | 05/03/2012 |
| 20120110417 | HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is init... | 05/03/2012 |
| 20120110414 | Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of inf... | 05/03/2012 |
| 20120110411 | Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of ... | 05/03/2012 |
| 20120084628 | RAM SINGLE EVENT UPSET (SEU) METHOD TO CORRECT ERRORS An error detection and correction (EDAC) circuit mitigates the effect of single event upsets (SEU) events in a redundant memory system. The EDAC circuit includes a first input for receiving first data and parity information stored by a first memory device and a second i... | 04/05/2012 |
| 20120084627 | DATA RECOVERY USING OUTER CODEWORDS STORED IN VOLATILE MEMORY Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface o... | 04/05/2012 |
| 20120072804 | DATA READ-OUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READING IN SEMICONDUCTOR MEMORY DEVICE A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense... | 03/22/2012 |
| 20120072803 | SEMICONDUCTOR STORAGE DEVICE, MEMORY CONTROL DEVICE, AND CONTROL METHOD OF SEMICONDUCTOR MEMORY According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in ea... | 03/22/2012 |
| 20120054580 | ERROR DETECTION CORRECTION METHOD AND SEMICONDUCTOR MEMORY APPARATUS In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability α from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check c... | 03/01/2012 |
| 20120047409 | SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks f... | 02/23/2012 |
| 20120030539 | ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a recor... | 02/02/2012 |
| 20120023385 | Method for adding redundancy data to a distributed data storage system and corresponding device. The invention proposes a method and device for adding redundancy data in a distributed data storage system. Among others, the invention allows to keep impact on network resources low through the use of coordinated regenerating codes according to the invention.... | 01/26/2012 |
| 20120023384 | SYSTEM AND METHOD OF DISTRIBUTIVE ECC PROCESSING Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-blo... | 01/26/2012 |
| 20120017136 | SYSTEMS AND METHODS FOR ENCODING INFORMATION FOR STORAGE IN AN ELECTRONIC MEMORY AND FOR DECODING ENCODED INFORMATION RETRIEVED FROM AN ELECTRONIC MEMORY Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the enc... | 01/19/2012 |
| 20120005558 | SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subse... | 01/05/2012 |
| 20120005557 | VIRTUAL COPY AND VIRTUAL WRITE OF DATA IN A STORAGE DEVICE A storage device with a memory and a controller, and a method of copying data on a storage device are provided to perform virtual copy and virtual write of data in a storage device without physically storing data in the storage device. The controller includes, or incorp... | 01/05/2012 |
| 20110320915 | METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshol... | 12/29/2011 |
| 20110320913 | RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. D... | 12/29/2011 |
| 20110314356 | VERIFYING INTEGRITY OF DATA STORED IN A DISPERSED STORAGE MEMORY A method for verifying integrity of data stored in dispersed storage memory begins by a processing module retrieving integrity information of the data that is stored as a set of forward error correction (FEC) encoded words in the dispersed storage memory and continues w... | 12/22/2011 |
| 20110314355 | ACCESSING DATA STORED IN A DISPERSED STORAGE MEMORY A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on t... | 12/22/2011 |
| 20110307760 | METHOD AND APPARATUS FOR PARALLEL PROCESSING IN A GIGABIT LDPC DECODER A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-den... | 12/15/2011 |
| 20110307761 | MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or mor... | 12/15/2011 |
| 20110302476 | Memory system and method of accessing a semiconductor memory device A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to... | 12/08/2011 |
| 20110302477 | Data Hardening to Compensate for Loss of Data Retention Characteristics in a Non-Volatile Memory Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a ... | 12/08/2011 |
| 20110302475 | Advanced Bitwise Operations and Apparatus in a Multi-Level System with Nonvolatile Memory A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read oper... | 12/08/2011 |
| 20110296276 | Dynamic Buffer Management In A NAND Memory Controller To Minimize Age Related Performance Degradation Due To Error Correction An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurali... | 12/01/2011 |
| 20110296258 | ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point... | 12/01/2011 |
| 20110289384 | MEMORY SYSTEM WITH PAGE-BASED ITERATIVE DECODING STRUCTURE AND PAGE-BASED ITERATIVE DECODING METHOD THEREOF A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful comp... | 11/24/2011 |
| 20110289381 | MEMORY SYSTEM THAT PROVIDES GUARANTEED COMPONENT-FAILURE CORRECTION WITH DOUBLE-ERROR CORRECTION The disclosed embodiments relate to a memory system that provides guaranteed component-failure correction and double-error correction. During operation, the memory system accesses a block of data, wherein each block of data in the memory system includes an array of bits... | 11/24/2011 |
| 20110289382 | Programmable LDPC code decoder and decoding method thereof A programmable LDPC (Low-Density Parity-Check) code decoder and decoding method thereof is disclosed. By combining at least one programmable switch and at least one memory unit to decode any quasi-cyclic-based parity check matrix, one can set the switch state of the pro... | 11/24/2011 |
| 20110289383 | RETRIEVING DATA FROM A DISPERSED STORAGE NETWORK IN ACCORDANCE WITH A RETRIEVAL THRESHOLD A method begins by a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN), wherein the set of encoded data slices represents data encoded using a dispersed storage error encoding function ... | 11/24/2011 |
| 20110289380 | METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power sta... | 11/24/2011 |
| 20110283163 | Method and System for Identifying Errors in Code A method for identifying errors in code is provided. The method may include rebuilding object dependencies from a heap dump, calculating memory usage of each object, identifying top consumers of memory by object class, analyzing how much memory each class consumes with ... | 11/17/2011 |
| 20110283164 | CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes mea... | 11/17/2011 |
| 20110276857 | DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory ... | 11/10/2011 |
| 20110276858 | MEMORY SYSTEM A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of... | 11/10/2011 |
| 20110271165 | SIGNAL LINE TO INDICATE PROGRAM-FAIL IN MEMORY Subject matter disclosed herein relates to a memory device and a method of operating same.... | 11/03/2011 |
