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| Application No. | Application Title | Issue Date |
| 20110289373 | Electornic Design Emulation Display Tool One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display simulation results related to the multiple processors, for example, as a co... | 11/24/2011 |
| 20110078526 | Method and Circuit Configuration for Simulating Fault States in a Control Unit A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a fault-generating circuit are used, the multiplexer being realized using a... | 03/31/2011 |
| 20100286797 | METHOD AND SYSTEM FOR TESTING SAFETY AUTOMATION LOGIC OF A MANUFACTURING CELL A method for testing the safety automation logic used in a manufacturing cell includes recording control signals of a safety-related component such as an E-Stop, light curtain, gate lock, or a safety mat using a host machine, and then disconnecting the component from th... | 11/11/2010 |
| 20100138710 | LOGIC VERIFICATION APPARATUS To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a d... | 06/03/2010 |
| 20100122132 | METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for r... | 05/13/2010 |
| 20100064191 | DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5... | 03/11/2010 |
| 20090287974 | Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual ope... | 11/19/2009 |
| 20090164861 | METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selectin... | 06/25/2009 |
| 20090119563 | METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to... | 05/07/2009 |
| 20090083600 | Systems and methods for critical node filtering of integrated circuits Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to identify... | 03/26/2009 |
| 20090077441 | METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test... | 03/19/2009 |
| 20090031181 | Automated root cause identification of logic controller failure A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic controll... | 01/29/2009 |
| 20080244347 | Automated Circuit Model Generator A method, system and program reduce ATPG processing times by eliminating non-value added cells in a circuit model that that is provided to an ATPG system. The elimination of non-value added cells results in a logically equivalent circuit model that is reduced in size fr... | 10/02/2008 |
| 20080126902 | Requirements-Based Test Generation This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality ... | 05/29/2008 |
| 20080115028 | METHOD AND SYSTEM FOR TEST VERIFICATION OF INTEGRATED CIRCUIT DESIGNS A method and system for verifying the design of an integrated circuit including an analog portion and a digital portion are disclosed. As one example, a method for verifying the design of an integrated circuit is disclosed, which includes the steps of generating an anal... | 05/15/2008 |
| 20080086668 | MODEL-BASED TESTING METHOD AND SYSTEM USING EMBEDDED MODELS A testing system and various methods involving testing of a device under test (DUT) use a device model to model a stimulus-response behavior of a the DUT. The testing system includes a device model of the DUT that is fitted to the stimulus-response behavior of the DUT a... | 04/10/2008 |
| 20080052586 | Low power decompression of test cubes Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety ... | 02/28/2008 |
| 20080040637 | DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the... | 02/14/2008 |
| 20070288822 | Timing-aware test generation and fault simulation Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In cert... | 12/13/2007 |
| 20070245197 | Method and apparatus for identifying paths having appropriate lengths for fault simulation A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a ... | 10/18/2007 |
| 20070226570 | SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to ... | 09/27/2007 |
| 20070220390 | Method and system for verifying equivalence of two representations of a stimulus pattern for testing a design A method for verifying the equivalence of two representations of a stimulus pattern for testing a design is disclosed. The method includes receiving a base pattern file representing the stimulus pattern in a first file format. A derivative pattern file in a second file ... | 09/20/2007 |
| 20070101226 | METHOD OF TEST PATTERN GENERATION IN IC DESIGN SIMULATION SYSTEM The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged v... | 05/03/2007 |
| 20070094562 | Apparatus and method for unified debug for simulation In one embodiment of the invention, a method for unified debug for simulation, includes: generating a transaction from a hardware verification language (HVL) testbench; copying signal states in the HVL testbench after the transaction is generated, wherein the signal sta... | 04/26/2007 |
| 20070079205 | Circuit simulation with decoupled self-heating analysis A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points ti and ti+1 based on predicted electrical responses of the devices at time point ti+1 and as ... | 04/05/2007 |
| 20070022349 | Test apparatus with tester channel availability identification Automated semiconductor device tester apparatus includes a plurality of tester channels for devices under test. The apparatus includes an automated switching module, for switching an unused operative tester channel in the place of any tester channel found to be malfunct... | 01/25/2007 |
| 20060282733 | Method and apparatus for processor emulation An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the per... | 12/14/2006 |
| 20060253760 | System and methods for processing software authorization and error feedback Software error feedback information, typically that associated with authorization failures due to operating system resource access checks, is automatically communicated to a software vendor with actions needed to prevent the software application error from occurring on ... | 11/09/2006 |
| 20060248425 | Delayed processing of site-aware objects A device is tested using a system that includes automatic test equipment (ATE) and a computer. At the ATE, the testing includes receiving data from the device, and processing the data to obtain processed data. At the computer, the testing includes executing a computer p... | 11/02/2006 |
| 20060248426 | Test access port Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor. ... | 11/02/2006 |
| 20060242524 | SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, a... | 10/26/2006 |
| 20060230326 | Method for re-using test cases through standardization and modularity A method is disclosed for creating test cases for simulating the design and operation of an integrated circuit having operational functionality that requires adherence to a multiplicity of operating rules, wherein the test cases are created in such a way that modularize... | 10/12/2006 |
| 20060212769 | Apparatus and method for testing codec software by utilizing parallel processes An apparatus for testing codec software includes a processor unit operative to execute a test program to read input data from a memory unit, to transform the input data according to transformation conditions by referring to data of the transformation conditions stored i... | 09/21/2006 |
| 20060200721 | Tester simulation system and tester simulation method using same It is an object of the invention to implement a tester simulation system capable of finding margins of respective expected value determining timings in a short time, and a tester simulation method using the same. The invention is an improvement of a tester simulation sy... | 09/07/2006 |
| 20060195746 | Variable clocked scan test improvements Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selec... | 08/31/2006 |
| 20060195745 | Methods and systems for repairing applications In accordance with the present invention, computer implemented methods and systems are provided that allow an application to automatically recover from software failures and attacks. Using one or more sensors, failures may be detected in the application. In response to ... | 08/31/2006 |
| 20060195744 | Method and apparatus to simulate automatic test equipment A virtual tester that simulates automatic test equipment (ATE). A translator converts program code of the ATE to pattern information and timing information. The virtual tester tests a software representation of a circuit, based on the program code of the ATE. The virtua... | 08/31/2006 |
| 20060184850 | Apparatus for preventing bus reset when removing a device from an IEEE 1394 network Disclosed is an apparatus for preventing bus reset when a node is removed in an Institute of Electrical and Electronics Engineers (IEEE) 1394 network. The apparatus includes a tone signal generator for generating a tone signal substantially identical to a tone signal ge... | 08/17/2006 |
| 20060179385 | Context-sensitive user help in a software-based development environment The invention relates to a method, a system and a computer program product for provision of user information within a software-based development environment for designing circuits and/or systems constructed from functional units. In order to provide help which is contex... | 08/10/2006 |
| 20060179384 | Double data rate serial encoder A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plur... | 08/10/2006 |
