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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Application No. | Application Title | Issue Date |
| 20110296266 | Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response sign... | 12/01/2011 |
| 20110138240 | ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to... | 06/09/2011 |
| 20110126065 | MICROPROCESSOR COMPRISING SIGNATURE MEANS FOR DETECTING AN ATTACK BY ERROR INJECTION A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data ... | 05/26/2011 |
| 20110060954 | SEMICONDUCTOR DEVICE AND METHOD FOR VALIDATING A STATE THEREOF A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and ... | 03/10/2011 |
| 20110047425 | On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further i... | 02/24/2011 |
| 20110047427 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providin... | 02/24/2011 |
| 20100017667 | Method and Device to Detect Failure of Static Pervasive Control Signals A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or ... | 01/21/2010 |
| 20090327824 | TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRATED CIRCUIT DEVICE A method, system and computer program product for performing device characterization Logic Built-In Self-Test (LBIST) in an IC device. Test parameters of the LBIST are saved in a memory of the IC device, and nominal operational parameters of the IC device are used to de... | 12/31/2009 |
| 20090282306 | ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to... | 11/12/2009 |
| 20090271675 | RADIATION INDUCED FAULT ANALYSIS A method of locating a defect of a failed semiconductor device which includes applying a test pattern to the failed semiconductor device and providing failed semiconductor device test responses as a pass signature, applying radiation to each of multiple locations of cir... | 10/29/2009 |
| 20090144594 | METHOD AND APPARATUS FOR DESCRIBING AND TESTING A SYSTEM-ON-CHIP The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to ... | 06/04/2009 |
| 20090144595 | BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock... | 06/04/2009 |
| 20090106614 | SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based... | 04/23/2009 |
| 20090094495 | MODULATION SIGNATURE TRIGGER A trigger generator and trigger method are provided for determining whether or not a signal under test matches a modulation signature. The modulation signature may be provided as a magnitude signature, a phase signature or both. When the magnitude values, phase values, ... | 04/09/2009 |
| 20090077439 | INTEGRATED CIRCUIT TEST METHOD AND TEST APPARATUS A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a ... | 03/19/2009 |
| 20090055696 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description... | 02/26/2009 |
| 20090031180 | Method for Discovering and Isolating Failure of High Speed Traces in a Manufacturing Environment A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manu... | 01/29/2009 |
| 20080263422 | CONTROL OF THE INTEGRITY OF A MEMORY EXTERNAL TO A MICROPROCESSOR A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signat... | 10/23/2008 |
| 20080263421 | Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circu... | 10/23/2008 |
| 20080256407 | PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM.... | 10/16/2008 |
| 20080155366 | DATA ACCESS METHOD FOR SERIAL BUS A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signals is transmitted on a clo... | 06/26/2008 |
| 20080126899 | Pattern controlled, full speed ATE compare capability for deterministic & non-deterministic IC data Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not... | 05/29/2008 |
| 20080115025 | Circuit and method operable in functional and diagnostic modes The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan... | 05/15/2008 |
| 20080109690 | TEST SYSTEM EMPLOYING TEST CONTROLLER COMPRESSING DATA, DATA COMPRESSING CIRCUIT AND TEST METHOD A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the... | 05/08/2008 |
| 20080104468 | Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.... | 05/01/2008 |
| 20080077834 | Deterministic Diagnostic Information Capture from Memory Devices with Built-in Self Test From a memory device comprising a memory circuit and a built-in self-test system (BIST), diagnostic information is deterministically obtained by using the BIST to perform a test sequence that tests the memory circuit. The test sequence comprises writing one or more test... | 03/27/2008 |
| 20080040638 | Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel... | 02/14/2008 |
| 20080034264 | Dynamic redundancy checker against fault injection A method and system for checking data stored in a memory of in a computer system is disclosed. The memory includes a plurality of memory addresses. The method and system include providing a signature generator coupled with the memory, providing a checker memory coupled ... | 02/07/2008 |
| 20070288136 | Method For Coupling A Control Unit To A Program For Modeling An Active Chain Diagnosis A method for coupling a control unit, in particular an engine control unit, for controlling a system, especially an engine, to a program for modeling an active chain diagnosis or to other programs for error analysis, having the following steps: within the scope of a fir... | 12/13/2007 |
| 20070226566 | ITERATIVE PROCESS FOR IDENTIFYING SYSTEMATICS IN DATA An iterative process for identifying systematics in data is provided. In general, a set of data is processed based on a signature definition to create a set of signature data. The set of signature data is then analyzed to identify common signatures. The set of signature... | 09/27/2007 |
| 20070208983 | Self learning signatures A system and method for monitoring processes corresponding to measurable values based on signatures associated with the measurable values is provided. The signatures can be created based on data from auxiliary data sets or auxiliary data sources. Additional monitoring i... | 09/06/2007 |
| 20070174750 | Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of... | 07/26/2007 |
| 20070150782 | METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the... | 06/28/2007 |
| 20070043992 | Pattern implementation technique A pattern implementation technique in which a pattern is defined as a software artifact that comprises a pattern signature representing one or more parameters of the pattern and a pattern implementation model representing one or more methods for expanding the pattern in... | 02/22/2007 |
| 20070038911 | Direct logic diagnostics with signature-based fault dictionaries Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received.... | 02/15/2007 |
| 20070033467 | Method and device for protecting a memory against attacks by error injection A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulat... | 02/08/2007 |
| 20070011534 | SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set w... | 01/11/2007 |
| 20070011533 | Method and apparatus for reducing number of transitions generated by linear feedback shift register A method for reducing the number of transitions generated by an LFSR is introduced. The transition monitoring window monitors the number of transitions occurring as random patterns generated from an LFSR are applied to a scan chain, and, if the number of transitions exc... | 01/11/2007 |
| 20060242518 | Method for verification of electronic circuit units, and an apparatus for carrying out the method The invention relates to a method for verification of electronic circuit units (101) which are contained in a circuit apparatus (100) with the operating state of the electronic circuit unit (101) to be verified being read by means of the circuit app... | 10/26/2006 |
| 20060200719 | System and method for performing logic failure diagnosis using multiple input signature register output streams A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a p... | 09/07/2006 |
