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| Application No. | Application Title | Issue Date |
| 20120131403 | MULTI-CHIP TEST SYSTEM AND TEST METHOD THEREOF A multi-chip test system and a method thereof utilize a Complex Programmable Logic Device (CPLD) to be connected in series to multiple chips having a Joint Test Action Group (JTAG) interface for function inspection. The test system includes a device to-be-tested and a c... | 05/24/2012 |
| 20120036406 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal termina... | 02/09/2012 |
| 20120023381 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.... | 01/26/2012 |
| 20120017129 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TA... | 01/19/2012 |
| 20110307749 | Low leakage boundary scan device design and implementation A boundary scan circuit comprising a freeze circuit and a transparency circuit provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an ... | 12/15/2011 |
| 20110289370 | OPTIMIZED JTAG INTERFACE An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availabil... | 11/24/2011 |
| 20110276847 | SHADOW ACCESS PORT METHOD AND APPARATUS The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port with... | 11/10/2011 |
| 20110271160 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2 | 11/03/2011 |
| 20110258502 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG tes... | 10/20/2011 |
| 20110225456 | COMMANDED JTAG TEST ACCESS PORT OPERATIONS The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and ... | 09/15/2011 |
| 20110214027 | 1149.1 TAP LINKING MODULES IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, buil... | 09/01/2011 |
| 20110209019 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... | 08/25/2011 |
| 20110209017 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... | 08/25/2011 |
| 20110209015 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration... | 08/25/2011 |
| 20110209016 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... | 08/25/2011 |
| 20110209018 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... | 08/25/2011 |
| 20110209014 | HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a ... | 08/25/2011 |
| 20110202808 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be use... | 08/18/2011 |
| 20110185243 | CONTROLLING TWO JTAG TAP CONTROLLERS WITH ONE SET OF JTAG PINS Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan ci... | 07/28/2011 |
| 20110185242 | INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access i... | 07/28/2011 |
| 20110185240 | EMBEDDED PROCESSOR Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a... | 07/28/2011 |
| 20110179325 | SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION A system for testing input/output pads of an integrated circuit includes boundary scan register chains, a test control unit and a test data processing unit. Input test data is provided to the test control unit, which then provides the test data to the test data processi... | 07/21/2011 |
| 20110161757 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. Th... | 06/30/2011 |
| 20110154140 | DIRECT SCAN ACCESS JTAG The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary dig... | 06/23/2011 |
| 20110145665 | ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and o... | 06/16/2011 |
| 20110119543 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data outp... | 05/19/2011 |
| 20110119542 | SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard,... | 05/19/2011 |
| 20110113298 | METHOD OF AND AN ARRANGEMENT FOR TESTING CONNECTIONS ON A PRINTED CIRCUIT BOARD A method of and an arrangement for testing connections on a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices mounted at the printed circuit board and comprising a boundary-scan register of boundary-sc... | 05/12/2011 |
| 20110099441 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2.<... | 04/28/2011 |
| 20110093751 | SYSTEM AND METHOD FOR SINGLE TERMINAL BOUNDARY SCAN An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second head... | 04/21/2011 |
| 20110087938 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be use... | 04/14/2011 |
| 20110087939 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan cir... | 04/14/2011 |
| 20110087940 | JTAG BUS COMMUNICATION METHOD AND APPARATUS The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC a... | 04/14/2011 |
| 20110072325 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TA... | 03/24/2011 |
| 20110055648 | SYSTEM AND A METHOD FOR TESTING CONNECTIVITY BETWEEN A FIRST DEVICE AND A SECOND DEVICE A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan re... | 03/03/2011 |
| 20110016366 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead <... | 01/20/2011 |
| 20110016365 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bounda... | 01/20/2011 |
| 20110010593 | SCAN ARCHITECTURE FOR FULL CUSTOM BLOCKS A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave... | 01/13/2011 |
| 20110010594 | INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access i... | 01/13/2011 |
| 20100299568 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... | 11/25/2010 |
