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| Application No. | Application Title | Issue Date |
| 20120131401 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register t... | 05/24/2012 |
| 20120131400 | SYSTEM AND METHOD FOR CORRECTING PROGRAMMING FAILURES IN A PROGRAMMABLE FUSE ARRAY A system for correcting programming failures in an M-bit primary array of programmable fuses. The address of the failed fuse is stored in a secondary fuse array. Correction logic coupled to the primary and secondary arrays propagates the programming states of the good f... | 05/24/2012 |
| 20120084612 | METHOD OF CONTROLLING A TEST MODE OF A CIRCUIT A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other out... | 04/05/2012 |
| 20120054567 | MULTIMEDIA DEVICE TEST SYSTEM A test system includes a supervisor unit coupled to a control interface, the control interface coupled to first and second test modules. Each test module may include a first logic module to test macro blocking errors; a second logic module to perform optical character r... | 03/01/2012 |
| 20120017128 | SYSTEM FOR TREE SEQUENCE TESTING OF A DEVICE AND METHOD FOR TREE SEQUENCE TESTING OF A DEVICE IN A TEST FRAMEWORK ARCHITECTURE A system comprises a test framework architecture for tree sequence testing of a device, comprising a plurality of hierarchical layers at least comprising an upmost layer and a lowest layer, each layer of the plurality of hierarchical layers comprising at least one of a ... | 01/19/2012 |
| 20120005545 | Computer product, verification support apparatus, and verification support method A computer-readable, non-transitory medium stores a program that causes a computer to execute detecting in a circuit-under-test, a change in a signal output from each circuit element on a transmission-side, during one clock cycle on a reception-side at an asynchronous l... | 01/05/2012 |
| 20120005547 | SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more... | 01/05/2012 |
| 20120005546 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bounda... | 01/05/2012 |
| 20110320893 | G-ODLAT On-die Logic Analyzer Trigger with Parallel Vector Finite State Machine An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, compri... | 12/29/2011 |
| 20110320894 | Surrogate Circuit For Testing An Interface A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The interface logic facilitates testing of the interface logic by attempting to perform the function on the s... | 12/29/2011 |
| 20110320895 | Test circuit for testing execution of a handshake protocol and method for testing execution of handshake protocol The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is asso... | 12/29/2011 |
| 20110271159 | TARGET DEVICE PROVIDING DEBUGGING FUNCTION AND TEST SYSTEM COMPRISING THE SAME A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block sup... | 11/03/2011 |
| 20110271156 | APPARATUS AND METHOD FOR TESTING SHADOW LOGIC A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential bloc... | 11/03/2011 |
| 20110258499 | SYSTEM FOR PERFORMING THE TEST OF DIGITAL CIRCUITS A system performs the test of a digital circuit. The system comprises a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execu... | 10/20/2011 |
| 20110246843 | ERROR DETECTION IN PRECHARGED LOGIC An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node i... | 10/06/2011 |
| 20110239066 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap doma... | 09/29/2011 |
| 20110219277 | System and Method of Test Mode Gate Operation A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The met... | 09/08/2011 |
| 20110185241 | Method and System for Packet Switch Based Logic Replication A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal dat... | 07/28/2011 |
| 20110161755 | Methods of Parametric Testing in Digital Circuits Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, ... | 06/30/2011 |
| 20110138238 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bounda... | 06/09/2011 |
| 20110126063 | METHOD FOR INSERTING TEST POINTS FOR LOGIC CIRCUITS AND LOGIC CIRCUIT TESTING APPARATUS This invention is intended to insert test points in a logic circuit under test in an effective manner. The logic circuit testing apparatus includes a fault estimation unit that estimates fault likelihoods for each of signal lines in a logic circuit in accordance with wi... | 05/26/2011 |
| 20110119542 | SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard,... | 05/19/2011 |
| 20110107162 | PARALLELIZATION METHOD, SYSTEM AND PROGRAM A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical represe... | 05/05/2011 |
| 20110099439 | AUTOMATIC DIVERSE SOFTWARE GENERATION FOR USE IN HIGH INTEGRITY SYSTEMS Systems, devices and methods of automatic diverse software generation are disclosed. In an embodiment, a method includes providing a base algorithm implementation related to a first hardware profile of a hardware resource, automatically generating a diverse algorithm im... | 04/28/2011 |
| 20110099440 | SYSTEMS AND METHODS FOR MEASURING SOFT ERRORS AND SOFT ERROR RATES IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft err... | 04/28/2011 |
| 20110087936 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circui... | 04/14/2011 |
| 20110078525 | Method and Apparatus of ATE IC Scan Test Using FPGA-Based System An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing... | 03/31/2011 |
| 20110078522 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE A self-test circuit includes a test circuit for processing input data and outputting output data having higher randomness than the input data; a storage unit for holding initial input data to be inputted to the test circuit when a self-test operation is performed on the... | 03/31/2011 |
| 20110060953 | TESTING MOBILE WIRELESS DEVICES DURING DEVICE PRODUCTION A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or a... | 03/10/2011 |
| 20110043243 | MEASUREMENT OF PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS CIRCUIT LEAKAGE CURRENT UNDER DIFFERENT STEADY STATE SWITCHING CONDITIONS A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selective... | 02/24/2011 |
| 20110047424 | INTEGRATED CIRCUIT INCLUDING A PROGRAMMABLE LOGIC ANALYZER WITH ENHANCED ANALYZING AND DEBUGGING CAPABILITES AND A METHOD THEREFOR An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an in... | 02/24/2011 |
| 20110047423 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an in... | 02/24/2011 |
| 20110041018 | MULTI-MODE PROGRAMMABLE SCAN FLOP A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled b... | 02/17/2011 |
| 20110041017 | On-Die Logic Analyzer For Semiconductor Die In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-d... | 02/17/2011 |
| 20110029828 | FAULT INJECTION DETECTOR IN AN INTEGRATED CIRCUIT A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a ... | 02/03/2011 |
| 20110022906 | METHOD AND SYSTEM FOR TEST POINT INSERTION It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic cones from a net list; generating an order for the plurality of logic cones b... | 01/27/2011 |
| 20100332927 | GENERIC DEBUG EXTERNAL CONNECTION (GDXC) FOR HIGH INTEGRATION INTEGRATED CIRCUITS A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate t... | 12/30/2010 |
| 20100325498 | MEMORY SYSTEM A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the ... | 12/23/2010 |
| 20100313087 | DEVICE TESTING ARCHITECTURE, METHOD AND SYSTEM A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The t... | 12/09/2010 |
| 20100275076 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME A semiconductor integrated circuit includes: a memory; a logic circuit configured to output an address signal for an address of the memory; and an address control circuit connected with the logic circuit and an address terminal of the memory, and configured to receive a... | 10/28/2010 |
