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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Application No. | Application Title | Issue Date |
| 20120131397 | SEMICONDUCTOR DEVICE HAVING TEST MODE AND METHOD OF CONTROLLING THE SAME When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the acti... | 05/24/2012 |
| 20120131396 | DEVICE AND METHOD FOR REPAIR ANALYSIS A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to... | 05/24/2012 |
| 20120110398 | DATA ERROR CHECK CIRCUIT, DATA ERROR CHECK METHOD, DATA TRANSMISSION METHOD USING DATA ERROR CHECK FUNCTION, SEMICONDUCTOR MEMORY APPARATUS AND MEMORY SYSTEM USING DATA ERROR CHECK FUNCTION Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted throug... | 05/03/2012 |
| 20120110399 | ERROR SCANNING IN FLASH MEMORY Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operation... | 05/03/2012 |
| 20120072788 | INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory e... | 03/22/2012 |
| 20120072791 | Debugger Based Memory Dump Using Built in Self Test A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include se... | 03/22/2012 |
| 20120072792 | MEMORY TESTER AND COMPILER WHICH MATCHES A TEST PROGRAM According to one embodiment, a memory tester is provided. The memory tester has first and second operation registers, a first selector, and first and second burst address generating circuits. The first operation register stores a first operation variable. The second ope... | 03/22/2012 |
| 20120072790 | On-Chip Memory Testing An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware... | 03/22/2012 |
| 20120072789 | MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY CONFIGURED TO FACILITATE PRODUCTION OF PRE-STRESSED INTEGRATED CIRCUITS AND METHODS Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn... | 03/22/2012 |
| 20120069689 | BUILT-IN SELF REPAIR FOR MEMORY A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the... | 03/22/2012 |
| 20120054564 | Method and apparatus to test memory using a regeneration mechanism A method and a system for testing memory blocks using a built-in-self-test (BIST) block using a regeneration mechanism. The method includes generation of a test pattern by executing a pre-defined algorithm to test a memory address of a memory block. The test pattern is ... | 03/01/2012 |
| 20120054566 | DRAM MEMORY CONTROLLER WITH BUILT-IN SELF TEST AND METHODS FOR USE THEREWITH An integrated circuit is interfaced with at least one dynamic random access memory (DRAM) via a memory interface. A plurality of user test options are received. The testing of the memory interface is controlled in accordance with the plurality of user test options. Test... | 03/01/2012 |
| 20120047410 | STORAGE DEVICE, CIRCUIT BOARD, LIQUID RESERVOIR AND SYSTEM A storage device according to some aspects of the invention includes a communication unit configured to perform processing for communication with a host apparatus; a storage unit configured to have a first memory area and a second memory area that store therein received... | 02/23/2012 |
| 20120047409 | SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks f... | 02/23/2012 |
| 20120047408 | SYSTEMS AND METHODS FOR MEMORY MANAGEMENT Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a qu... | 02/23/2012 |
| 20120047411 | DETERMINING DATA VALID WINDOWS IN A SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the... | 02/23/2012 |
| 20120011409 | DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured ... | 01/12/2012 |
| 20110320891 | Driving Method of Electronic Device A method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power sequentially supplied from a contactless power feeding device, and a plurality of loads to which power is sequentially supp... | 12/29/2011 |
| 20110307747 | MEMORY TESTING SYSTEM An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block co... | 12/15/2011 |
| 20110302469 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array, a write control circuit, a latch circuit, an address control circuit, a scan control circuit, and an address latch circuit. The write control circuit executes write and... | 12/08/2011 |
| 20110302467 | Memory test system with advance features for completed memory system In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedbac... | 12/08/2011 |
| 20110302468 | Memory system and method of accessing a semiconductor memory device A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to... | 12/08/2011 |
| 20110296259 | TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry;... | 12/01/2011 |
| 20110276844 | METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is d... | 11/10/2011 |
| 20110276846 | UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in... | 11/10/2011 |
| 20110276845 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE TO DIAGNOSE TEMPERATURE-INDUCED MEMORY ERRORS Example methods, apparatus and articles of manufacture to diagnose temperature-induced memory errors are disclosed. A disclosed example method to diagnose a temperature-induced memory error includes detecting a memory error associated with a memory device, and writing a... | 11/10/2011 |
| 20110271157 | TEST CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memo... | 11/03/2011 |
| 20110271156 | APPARATUS AND METHOD FOR TESTING SHADOW LOGIC A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential bloc... | 11/03/2011 |
| 20110264969 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control ci... | 10/27/2011 |
| 20110252284 | OPTIMIZATION OF PACKET BUFFER MEMORY UTILIZATION A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for ... | 10/13/2011 |
| 20110239061 | SYSTEMS AND METHODS FOR RETRIEVING DATA Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If suffic... | 09/29/2011 |
| 20110239062 | SEMICONDUCTOR DEVICE A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first regist... | 09/29/2011 |
| 20110239065 | RUN-TIME TESTING OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY Systems and methods are disclosed for performing run-time tests on a non-volatile memory (“NVM”), such as flash memory. The run-time tests may be tests that are performed on the NVM while the NVM can be operated by an end user (as opposed to during a manufacturing p... | 09/29/2011 |
| 20110231717 | SEMICONDUCTOR MEMORY DEVICE Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through... | 09/22/2011 |
| 20110231716 | DIAGNOSIS FLOW FOR READ-ONLY MEMORIES A system and a method for diagnosis flow for a read-only memory (ROM) includes determining whether a window of the ROM is faulty, based on a pre-computed signature and a computed signature corresponding to the window. Based on the determination, the size of the window i... | 09/22/2011 |
| 20110231718 | MEMORY REPAIR A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.... | 09/22/2011 |
| 20110219276 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS, AND A NON-TRANSITORY COMPUTER-READABLE MEDIUM HAVING A SEMICONDUCTOR INTEGRATED CIRCUIT TESTING PROGRAM An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test ... | 09/08/2011 |
| 20110209012 | Method and apparatus for optimizing address generation for simultaneously running proximity-based BIST algorithms The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column ... | 08/25/2011 |
| 20110186631 | METHOD FOR SETTING OPERATING FREQUENCY OF MEMORY CARD AND RELATED CARD READING APPARATUS A method for setting an operating frequency of a memory card includes the following steps: performing an operating frequency adjusting flow to select a target operating frequency, and utilizing the target operating frequency to set the operating frequency of the memory ... | 08/04/2011 |
| 20110185239 | SEMICONDUCTOR TESTING APPARATUS AND METHOD The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell ar... | 07/28/2011 |
