Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131395 | METHOD AND APPARATUS FOR REDUCING BIT ERRORS An apparatus and method for reduction of bit errors in continuous data transmission via a data transmission medium comprising. The apparatus (1) comprises a monitoring unit (1A) for monitoring of transceiver parameters of at least one transceiver (3... | 05/24/2012 |
| 20120072785 | BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the se... | 03/22/2012 |
| 20120072786 | USE OF HASHING FUNCTION TO DISTINGUISH RANDOM AND REPEAT ERRORS IN A MEMORY SYSTEM One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. A... | 03/22/2012 |
| 20120072784 | CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also includ... | 03/22/2012 |
| 20120042219 | States Encoding in Multi-Bit Flash Cells for Optimizing Error Rate Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, ... | 02/16/2012 |
| 20120033320 | Systems and Methods for Dynamic Scaling in a Read Data Processing System Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first ... | 02/09/2012 |
| 20120030527 | SEMICONDUCTOR MEMORY DEVICE Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of err... | 02/02/2012 |
| 20120030529 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a no... | 02/02/2012 |
| 20120030528 | SEMICONDUCTOR STORAGE DEVICE As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitorin... | 02/02/2012 |
| 20120002561 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION USED IN COMMUNICATION SYSTEM HAVING TIME SLOTS An apparatus used in a communication system having a plurality of time slots includes a signal processing circuit, a signal detector, and a controlling circuit. The signal processing circuit receives an input signal. The signal detector detects the input signal to gener... | 01/05/2012 |
| 20110302466 | SIGNAL TRANSMISSION DEVICE FOR ELEVATOR Each of a control panel node 2 and an input/output node 3 has a safety data processing unit 7 and a high reliability communication unit 8. At the time of transmission, the safety data processing unit 7 creates a safety data packet incl... | 12/08/2011 |
| 20110296258 | ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point... | 12/01/2011 |
| 20110271155 | Method and Apparatus for Measuring Symbol and Bit Error Rates Independent of Disparity Errors A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparat... | 11/03/2011 |
| 20110264790 | Method And Apparatus For Measuring Business Transaction Performance A method for measuring business transaction performance, includes the steps of, at a top-level component, assigning a correlation tag and original time stamp to a server request, passing the original time stamp with any server requests from the top-level component to on... | 10/27/2011 |
| 20110264968 | CABLE WITH FIELD-WRITEABLE MEMORY A method includes monitoring a use of a cable assembly that includes a communication cable terminated by a termination module. Data indicative of the use is written to a writeable non-volatile memory in the termination module. The use of the cable assembly is acted upon... | 10/27/2011 |
| 20110258496 | DATA READING METHOD, MEMORY STORAGE APPARATUS AND MEMORY CONTROLLER THEREOF A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physi... | 10/20/2011 |
| 20110258495 | METHODS OF CALCULATING COMPENSATION VOLTAGE AND ADJUSTING THRESHOLD VOLTAGE AND MEMORY APPARATUS AND CONTROLLER Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volat... | 10/20/2011 |
| 20110239061 | SYSTEMS AND METHODS FOR RETRIEVING DATA Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If suffic... | 09/29/2011 |
| 20110225470 | Serial Interface Device Built-In Self Test A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The... | 09/15/2011 |
| 20110191645 | METHOD AND APPARATUS FOR ADJUSTING NUMBER OF ITERATIONS IN ITERATIVE DECODING PROCEDURE In a method of determining an iteration value for an iterative decoding process of a hard disk drive, a bit error rate (BER) of a digital signal is measured in multiple iterations. A difference is calculated between BERs of consecutive iterations, and the calculated dif... | 08/04/2011 |
| 20110191644 | Method and apparatus for SAS speed adjustment A method for maintaining reliable communication on a bidirectional communication link is provided. A receiver on the bidirectional communication link detects an error and maintains a count of detected errors. The transmitter on the bidirectional communication link polls... | 08/04/2011 |
| 20110167297 | CLOCK-DATA-RECOVERY TECHNIQUE FOR HIGH-SPEED LINKS A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal bas... | 07/07/2011 |
| 20110145663 | Read level control apparatuses and methods Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit e... | 06/16/2011 |
| 20110131444 | SYSTEMS AND METHODS FOR LOW WEAR OPERATION OF SOLID STATE MEMORY This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data stor... | 06/02/2011 |
| 20110119536 | Estimating Bit Error Rate Performance of Signals A system for estimating bit error rates (BER) may include using a normalization factor that scales a BER to substantially normalize a Q-scale for a distribution under analysis. A normalization factor may be selected, for example, to provide a best linear fit for both ri... | 05/19/2011 |
| 20110110402 | ERROR REPORTING IN MULTI-CARRIER SIGNAL COMMUNICATION In a communication device, a multi-carrier signal with at least one group of signal carriers is received from a communication connection. For each of the signal carriers, at least one individual error value is evaluated or generated. From the individual error values, a ... | 05/12/2011 |
| 20110113294 | TUNABLE EARLY-STOPPING FOR DECODERS A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computin... | 05/12/2011 |
| 20110107160 | TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident ... | 05/05/2011 |
| 20110099437 | Loss Tolerant Transmission Control Protocol A particular device includes a transmitter. The transmitter is adapted to estimate a packet erasure rate for packets of a data window to be transmitted to a receiver. The transmitter is adapted to determine a number of proactive forward error control (FEC) packets for t... | 04/28/2011 |
| 20110087933 | POWER CONSUMPTION IN LDPC DECODER FOR LOW-POWER APPLICATIONS This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in... | 04/14/2011 |
| 20110055643 | RECEIVER POWER SAVING VIA BLOCK CODE FAILURE DETECTION A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least o... | 03/03/2011 |
| 20110035634 | STORAGE DEVICE WITH ADAPTIVE ERROR-CORRECTING CODE FOR IMPROVED AREAL EFFICIENCY A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors ... | 02/10/2011 |
| 20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits incl... | 02/03/2011 |
| 20110022904 | MODEM-ASSISTED BIT ERROR CONCEALMENT FOR AUDIO COMMUNICATIONS SYSTEMS Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one charact... | 01/27/2011 |
| 20110010592 | INFORMATION TRANSMITTING METHOD AND INFORMATION TRANSMITTING SYSTEM Information transmitting arrangements for transmitting information through a plurality of base stations from a master station to a plurality of slave stations which communicate with the base stations.... | 01/13/2011 |
| 20100332922 | METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. Th... | 12/30/2010 |
| 20100318861 | MODE SELECTION FOR DATA TRANSMISSION IN WIRELESS COMMUNICATION CHANNELS BASED ON STATISTICAL PARAMETERS A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is bas... | 12/16/2010 |
| 20100313084 | SEMICONDUCTOR STORAGE DEVICE As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitorin... | 12/09/2010 |
| 20100306598 | Operating Computer Memory Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory error... | 12/02/2010 |
| 20100303038 | Method for optimizing network structures in radio networks In WirelessHART networks, mechanisms are already known that ensure a practical composition of a radio network with regard to its structure, whereby for this purpose, so-called health reports are also utilized, which are transmitted by the individual nodes to a central m... | 12/02/2010 |
