Class 713/401 - Using delay

Subclass of Class 713 - Electrical computers and digital processing systems: support
Definition: Subject matter wherein the clock or timing signals, timing
No. of applications: 133
Last issue date: 03/22/2012

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Application No.	Application Title	Issue Date
20120072759	Timing Error Correction System and Method A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the...	03/22/2012
20120047388	Adjustable Byte Lane Offset For Memory Module to Reduce Skew Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in ...	02/23/2012
20120047389	NON-VOLATILE MEMORY DEVICES FOR OUTPUTTING DATA USING DOUBLE DATA RATE (DDR) OPERATIONS AND METHODS OF OPERATING THE SAME A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization...	02/23/2012
20110320851	PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation o...	12/29/2011
20110296110	Critical Word Forwarding with Adaptive Prediction In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory contro...	12/01/2011
20110289339	Semiconductor device A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on f...	11/24/2011
20110271133	ADDRESS OUTPUT TIMING CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a...	11/03/2011
20110258475	Dynamically Calibrated DDR Memory Controller A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a ...	10/20/2011
20110252265	DELAY CONTROLLER, CONTROL METHOD, AND COMMUNICATION SYSTEM A delay controller includes an acquiring section that acquires synchronization timings indicating timings when a plurality of controllers, which control via a line a plurality of transmitters that transmit data, synchronously control the transmitters, a determining sect...	10/13/2011
20110246809	Synchronization of Converters Having Varying Group-Delays in a Measurement System An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding to the ADC largely transparent to the end-user of the ADC. Therefore, mu...	10/06/2011
20110219256	SYNCHRONIZATION DEVICES HAVING INPUT/OUTPUT DELAY MODEL TUNING ELEMENTS IN SIGNAL PATHS TO PROVIDE TUNING CAPABILITIES TO OFFSET SIGNAL MISMATCH Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in t...	09/08/2011
20110202786	Stalling synchronisation circuits in response to a late data signal A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged betwee...	08/18/2011
20110185216	Time Synchronization Method and System for Multicore System A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; selecting a core...	07/28/2011
20110185215	Single-Wire Serial Interface A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circui...	07/28/2011
20110161715	INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift...	06/30/2011
20110131440	SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first ...	06/02/2011
20110131439	Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as...	06/02/2011
20110126038	TIME DELAY COMPENSATION IN POWER SYSTEM CONTROL A method and controller are provided for the compensation of time delays in remote feedback signals in power system control. The method includes converting the time delay into a phase shift and calculating four compensation angles from the phase shift. The optimal compe...	05/26/2011
20110119519	METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array o...	05/19/2011
20110119518	METHOD FOR PROVIDING A GUARANTEED PLAYOUT RATE A method for delivering data to first and second processes comprising: identifying a first process communicatively connected to a first data access port; identifying a second process communicatively connected to a second data access port; identifying a data-throughput r...	05/19/2011
20110106335	MICROCONTROLLER, CONTROL SYSTEM AND DESIGN METHOD OF MICROCONTROLLER Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization w...	05/05/2011
20110099409	DELAYING ONE-SHOT SIGNAL OBJECTS A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be c...	04/28/2011
20110087913	TECHNIQUES FOR MANAGING LOWER POWER STATES FOR DATA LINKS Techniques for managing lower power states for data links are described. An apparatus may comprise a memory unit to store a device connection manager for a controller of a bi-directional serial link connected to a device. The apparatus may comprise a processor operative...	04/14/2011
20110072296	INFORMATION PROCESSING APPARATUS, DATA RECEPTION DEVICE AND METHOD OF CONTROLLING THE INFORMATION PROCESSING APPARATUS A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmi...	03/24/2011
20110060934	METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a s...	03/10/2011
20110040997	SYNCHRONIZATION OF CLOCKS IN AUTONOMOUS COMPONENTS OF AN MR SYSTEM AND SYNCHRONOUS EXECUTION OF COMMANDS IN THOSE COMPONENTS In a device and a method to execute commands in components of an imaging system, in particular of a magnetic resonance tomography system, local clocks in the components are temporally synchronized, commands, including a respective command execution time specification wh...	02/17/2011
20110029762	SEMICONDUCTOR DEVICE PERFORMING SERIAL PARALLEL CONVERSION A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stag...	02/03/2011
20110022873	SYSTEM WITH POWER SAVING DELAY LOCKED LOOP CONTROL The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not im...	01/27/2011
20110022872	Apparatus for and method of generating a time reference In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation s...	01/27/2011
20100293406	METHOD TO CALIBRATE START VALUES FOR WRITE LEVELING IN A MEMORY SYSTEM A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime...	11/18/2010
20100293405	INTEGRATED CIRCUIT WITH REDUCED ELECTROMAGNETIC INTERFERENCE INDUCED BY MEMORY ACCESS AND METHOD FOR THE SAME The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random code...	11/18/2010
20100257397	ACTIVE TRAINING OF MEMORY COMMAND TIMING Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller....	10/07/2010
20100217928	Semiconductor Memory Asynchronous Pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals ...	08/26/2010
20100194421	TEST EQUIPMENT AND TEST METHOD Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the t...	08/05/2010
20100199006	DATA TRANSFER DEVICE AND DATA TRANSFER METHOD To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A m...	08/05/2010
20100199117	TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock sign...	08/05/2010
20100180141	METHOD OF DYNAMICALLY ADJUSTING SIGNAL DELAY TIME OF CIRCUIT SYSTEM A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a si...	07/15/2010
20100174830	SYNCHRONIZING MULTIPLE SYSTEM CLOCKS Techniques are disclosed for synchronizing multiple clock sources of a system, and may include: determining time of a first clock at a first and second time instants; determining time of a second clock at a third time instant occurring between the first and second time ...	07/08/2010
20100169696	PROCESSOR SYSTEM EMPLOYING A SIGNAL ACQUISITION MANAGING DEVICE AND SIGNAL ACQUISITION MANAGING DEVICE A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate...	07/01/2010
20100153766	MEMORY CONTROLLER AND DEVICE WITH DATA STROBE CALIBRATION A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupl...	06/17/2010

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Class 713/401 - Using delay