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Walt Disney was no Mickey Mouse inventor. He devised a serious animation camera which he patented. With the device, his company created "Snow White".
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| Application No. | Application Title | Issue Date |
| 20120042151 | PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequ... | 02/16/2012 |
| 20110179308 | Auxiliary circuit structure in a split-lock dual processor system A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1 checks the operation of the other processor 4-0 and a spl... | 07/21/2011 |
| 20100332799 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD According to an aspect of the present invention, there is provided an information processing apparatus including: a first processor; a second processor that has an information processing capability and a power consumption higher than those of the first processor; a temp... | 12/30/2010 |
| 20100169609 | Method for optimizing voltage-frequency setup in multi-core processor systems A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational par... | 07/01/2010 |
| 20100082943 | DYNAMIC RECONFIGURATION SUPPORT APPARATUS, DYNAMIC RECONFIGURATION SUPPORT METHOD, AND COMPUTER PRODUCT An apparatus controls a circuit having rewritable processor elements and includes an acquiring unit that acquires information concerning a first task under execution by the circuit; a reading unit that, when the information concerning the first task is acquired, reads f... | 04/01/2010 |
| 20100031005 | Instruction Encoding For System Register Bit Set And Clear An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) ... | 02/04/2010 |
| 20090327656 | EFFICIENCY-BASED DETERMINATION OF OPERATIONAL CHARACTERISTICS Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences,... | 12/31/2009 |
| 20090100250 | SWITCHING BETWEEN MULTIPLE SOFTWARE ENTITIES USING DIFFERENT OPERATING MODES OF A PROCESSOR The computer program includes a virtualization software that is executable on the new processor in the legacy mode. The new processor includes a legacy instruction set for a legacy operating mode and a new instruction set for a new operation mode. The switching includes... | 04/16/2009 |
| 20090083520 | DATA PROCESSING DEVICE Provided is a data processing device that can prevent data used by a program from being used by another program in an unauthorized manner, regardless of the quality of the programs. The data processing device includes: a CPU 0201 for executing programs; and an un... | 03/26/2009 |
| 20090077349 | METHOD OF MANAGING INSTRUCTION CACHE AND PROCESSOR USING THE METHOD A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during... | 03/19/2009 |
| 20080263324 | DYNAMIC CORE SWITCHING A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric ... | 10/23/2008 |
| 20080209170 | Method and Device for Performing Switchover Operations and for Signal Comparison in a Computer System Having at Least Two Processing Units A method for switchover and for signal comparison is used in a computer system having at least two processing units, a switchover device being provided, and a switch taking place between at least two operating modes, and a comparison device being provided; and a first o... | 08/28/2008 |
| 20080168258 | Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method u... | 07/10/2008 |
| 20080162890 | COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing ... | 07/03/2008 |
| 20080072014 | Low Power Dual Processor Architecture for Multi Mode Devices A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, th... | 03/20/2008 |
| 20080059768 | Method and Apparatus for Communicating a Bit Per Half Clock Cycle over at Least One Pin of an SPI Bus Various embodiments increase the speed of communication over an SPI bus by communicating a bit per half clock cycle over at least one pin of an SPI bus. ... | 03/06/2008 |
| 20080052494 | Method And Device For Operand Processing In A Processing Unit A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is p... | 02/28/2008 |
| 20070016759 | System and method of controlling multiple program threads within a multithreaded processor A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first... | 01/18/2007 |
| 20060200333 | Optimizing active decision making using simulated decision making A method and a computer implemented system for improving an active decision making process by using a simulation model of the decision making process. The simulation model is used to evaluate the impact of alternative decisions at a choice point, in order to select one ... | 09/07/2006 |
| 20060149927 | Processor capable of multi-threaded execution of a plurality of instruction-sets A processor (100) capable of receiving a plurality of instructions sets from at least one memory (50), and capable of multi-threaded execution of the plurality of instruction sets. The processor includes at least one decoder (130) capable of decodin... | 07/06/2006 |
| 20060004988 | Single bit control of threads in a multithreaded multicore processor A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status... | 01/05/2006 |
| 20050251650 | Dynamic endian switching The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may receive a signal from the processor that determines what the endian-ness shoul... | 11/10/2005 |
