Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Application No. | Application Title | Issue Date |
| 20120131316 | METHOD AND APPARATUS FOR IMPROVED SECURE COMPUTING AND COMMUNICATIONS A method and apparatus are disclosed that may comprise applying compact markup notation to a general recursive computing system including hardware and software components, the compact markup notation defining things, places, paths, actions and causes within at least one... | 05/24/2012 |
| 20120023316 | PARALLEL LOOP MANAGEMENT The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of in... | 01/26/2012 |
| 20110302397 | Method and Apparatus for Improved Secure Computing and Communications A computing and communications system and method may comprise a primitive recursive function computing engine including an instruction set architecture prohibiting loop operations that continue for an indefinite time. The system and method may further comprise the instr... | 12/08/2011 |
| 20110238957 | SOFTWARE CONVERSION PROGRAM PRODUCT AND COMPUTER SYSTEM According to one embodiment, a software conversion program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer system including a host processor and one or more accelerator processors, causes... | 09/29/2011 |
| 20110219222 | Building Approximate Data Dependences with a Moving Window Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a portion of code. The mechanisms receive a memory access of an iteration o... | 09/08/2011 |
| 20110161643 | Runtime Extraction of Data Parallelism Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterati... | 06/30/2011 |
| 20110161642 | Parallel Execution Unit that Extracts Data Parallelism at Runtime Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a t... | 06/30/2011 |
| 20110107071 | SYSTEM AND METHOD FOR USING A BRANCH MIS-PREDICTION BUFFER A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct... | 05/05/2011 |
| 20110072215 | Cache system and control method of way prediction for cache memory A cache device according to an exemplary aspect of the present invention includes a way information buffer that stores way information that is a result of selecting a way in an instruction that accesses a cache memory; and a control unit that controls a storage processi... | 03/24/2011 |
| 20110072251 | PILE PROCESSING SYSTEM AND METHOD FOR PARALLEL PROCESSORS A system, method and computer program product are provided for processing exceptions. Initially, computational operations are processed in a loop. Moreover, exceptions are identified and stored while processing the computational operations. Such exceptions are then proc... | 03/24/2011 |
| 20110055445 | Digital Signal Processing Systems A signal processing system may include a multiply-accumulate (MAC) unit to generate output data by performing multiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where the MAC unit is pipelined to enable it to ... | 03/03/2011 |
| 20110029763 | BRANCH PREDICTOR FOR SETTING PREDICATE FLAG TO SKIP PREDICATED BRANCH INSTRUCTION EXECUTION IN LAST ITERATION OF LOOP PROCESSING A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop pro... | 02/03/2011 |
| 20100306516 | INFORMATION PROCESSING APPARATUS AND BRANCH PREDICTION METHOD An information processor includes a first recording unit which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent branch instruction, a computation of the most recent branch instruction hav... | 12/02/2010 |
| 20100299509 | SIMULATION SYSTEM, METHOD AND PROGRAM A computer-implemented pipeline execution system, method, and program product for executing loop processing in a multi-core or a multiprocessor computing environment, where the loop processing includes multiple function blocks in a multiple-stage pipeline manner. The sy... | 11/25/2010 |
| 20100287550 | Runtime Dependence-Aware Scheduling Using Assist Thread A runtime dependence-aware scheduling of dependent iterations mechanism is provided. Computation is performed for one or more iterations of computer executable code by a main thread. Dependence information is determined for a plurality of memory accesses within the comp... | 11/11/2010 |
| 20100281240 | Program Code Simulator A system and method for facilitating simulation of a computer program. A program representation is generated from a computer program. A simulation of the program is performed. Simulation may include applying heuristics to determine program flow for selected instructions... | 11/04/2010 |
| 20100235612 | MACROSCALAR PROCESSOR ARCHITECTURE A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one o... | 09/16/2010 |
| 20100211762 | Mechanism for Efficient Implementation of Software Pipelined Loops in VLIW Processors A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction... | 08/19/2010 |
| 20100199076 | COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the ho... | 08/05/2010 |
| 20100185839 | APPARATUS AND METHOD FOR SCHEDULING INSTRUCTION An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When s... | 07/22/2010 |
| 20100180102 | Enhancing processing efficiency in large instruction width processors A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the process... | 07/15/2010 |
| 20100175056 | COMPILER APPARATUS WITH FLEXIBLE OPTIMIZATION A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” con... | 07/08/2010 |
| 20100169612 | Data-Processing Unit for Nested-Loop Instructions A data-processing unit has a fetching circuitry (20) and execution circuitry (30a, 30b). The data-processing unit has an instruction set comprising a nested-loop instruction. The fetching circuitry is arranged to fetch the nested-loop ... | 07/01/2010 |
| 20100153688 | APPARATUS AND METHOD FOR DATA PROCESS An exemplary aspect of the present invention is a data processing apparatus for processing a loop in a pipeline that includes an instruction memory and a fetch circuit that fetches an instruction stored in the instruction memory. The fetch circuit includes an instructio... | 06/17/2010 |
| 20100122066 | INSTRUCTION METHOD FOR FACILITATING EFFICIENT CODING AND INSTRUCTION FETCH OF LOOP CONSTRUCT Instruction set techniques have been developed to identify explicitly the beginning of a loop body and to code a conditional loop-end in ways that allow a processor implementation to efficiently manage an instruction fetch buffer and/or entries in an instruction cache. ... | 05/13/2010 |
| 20100122069 | Macroscalar Processor Architecture A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and e... | 05/13/2010 |
| 20100064106 | DATA PROCESSOR AND DATA PROCESSING SYSTEM The present invention provides a data processor capable of automatically discriminating a loop program and performing a reduction in power by size-variable lock control on an instruction buffer. The instruction buffer of the data processor includes a buffer controller f... | 03/11/2010 |
| 20100058039 | INSTRUCTION FETCH PIPELINE FOR SUPERSCALAR DIGITAL SIGNAL PROCESSORS AND METHOD OF OPERATION THEREOF A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruct... | 03/04/2010 |
| 20100049958 | METHOD FOR EXECUTING AN INSTRUCTION LOOPS AND A DEVICE HAVING INSTRUCTION LOOP EXECUTION CAPABILITIES A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; ... | 02/25/2010 |
| 20100005276 | INFORMATION PROCESSING DEVICE AND METHOD OF CONTROLLING INSTRUCTION FETCH An information processing device includes an instruction fetch unit, an instruction buffer, an instruction executing unit, and an instruction fetch control unit. The instruction fetch unit supplies a fetch address to an instruction memory. The instruction buffer stores ... | 01/07/2010 |
| 20090327674 | Loop Control System and Method Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to de... | 12/31/2009 |
| 20090262877 | Computation spreading utilizing dithering for spur reduction in a digital phase lock loop A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to seq... | 10/22/2009 |
| 20090265534 | Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multip... | 10/22/2009 |
| 20090259832 | RETARGETTING AN APPLICATION PROGRAM FOR EXECUTION BY A GENERAL PURPOSE PROCESSOR One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Port... | 10/15/2009 |
| 20090254738 | OBFUSCATION DEVICE, PROCESSING DEVICE, METHOD, PROGRAM, AND INTEGRATED CIRCUIT THEREOF It is an object of the present invention to provide an obfuscation device that can achieve both sufficient obfuscation and the appropriate instruction block to be executed. In the obfuscation device, a first instruction generating unit, for each of the first process and... | 10/08/2009 |
| 20090235052 | Data Processing Device and Electronic Equipment A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plu... | 09/17/2009 |
| 20090228677 | DIGITAL DATA PROCESSING METHOD AND SYSTEM A method and system for processing generic formatted data, including first data describing a sequence of generic operations without any loops, in view of providing specific formatted data, for a determined platform including Q processor(s) and at least one memory, the p... | 09/10/2009 |
| 20090217017 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses sto... | 08/27/2009 |
| 20090158018 | Method and System for Auto Parallelization of Zero-Trip Loops Through the Induction Variable Substitution A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known a... | 06/18/2009 |
| 20090150658 | Processor and Signal Processing Method This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch ins... | 06/11/2009 |
