Class 712/23 - Superscalar

Subclass of Class 712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
Definition: Subject matter comprising an architecture which determines
No. of applications: 31
Last issue date: 07/07/2011

Application No.	Application Title	Issue Date
20110167241	SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array ha...	07/07/2011
20110035570	MICROPROCESSOR WITH ALU INTEGRATED INTO STORE UNIT A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store u...	02/10/2011
20110035569	MICROPROCESSOR WITH ALU INTEGRATED INTO LOAD UNIT A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The loa...	02/10/2011
20100318772	SUPERSCALAR REGISTER-RENAMING FOR A STACK-ADDRESSED ARCHITECTURE A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP) stack specifier. The combinatorial logic for operand translation of N FP i...	12/16/2010
20090228729	Selective Power-Down For High Performance CPU/System A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to b...	09/10/2009
20090172359	PROCESSING PIPELINE HAVING PARALLEL DISPATCH AND METHOD THEREOF One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, ...	07/02/2009
20090138674	ELECTRONIC SYSTEM FOR CHANGING NUMBER OF PIPELINE STAGES OF A PIPELINE An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal....	05/28/2009
20090019257	Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions,...	01/15/2009
20080320274	Age matrix for queue dispatch order An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch i...	12/25/2008
20080313425	Enhanced Load Lookahead Prefetch in Single Threaded Mode for a Simultaneous Multithreaded Microprocessor A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency miss...	12/18/2008
20080313424	METHOD AND APPARATUS FOR SPATIAL REGISTER PARTITIONING WITH A MULTI-BIT CELL REGISTER FILE There is provided a multi-bit storage cell for a register file. The storage cell includes a first set of storage elements for a vector slice. Each storage element respectively corresponds to a particular one of a plurality of thread sets for the vector slice. The storag...	12/18/2008
20080270749	Instruction issue control within a multi-threaded in-order superscalar processor A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is ...	10/30/2008
20080263318	Timed ports A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic conf...	10/23/2008
20080244224	Scheduling a direct dependent instruction In one embodiment, the present invention includes an apparatus having an instruction selector to select an instruction, where the selector is to store a dependent indicator to indicate a direct dependent consumer instruction of a producer instruction, a decode logic cou...	10/02/2008
20080244223	BRANCH PRUNING IN ARCHITECTURES WITH SPECULATION SUPPORT According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions e...	10/02/2008
20080235491	Techniques for Maintaining a Stack Pointer A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack ...	09/25/2008
20080172546	DIGITAL SIGNAL PROCESSOR A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping...	07/17/2008
20080082788	POINTER-BASED INSTRUCTION QUEUE DESIGN FOR OUT-OF-ORDER PROCESSORS A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access memory, a mapping table, and a multiple wake-up table. Instructions alloc...	04/03/2008
20080005533	A METHOD TO REDUCE THE NUMBER OF LOAD INSTRUCTIONS SEARCHED BY STORES AND SNOOPS IN AN OUT-OF-ORDER PROCESSOR A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing...	01/03/2008
20070113047	RISC microprocessor architecture implementing multiple typed register sets A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer...	05/17/2007
20070089112	BARREL-INCREMENTER-BASED ROUND-ROBIN APPARATUS AND INSTRUCTION DISPATCH SCHEDULER EMPLOYING SAME FOR USE IN MULTITHREADING MICROPROCESSOR An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requesters may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value specifyi...	04/19/2007
20070079109	Simulation apparatus and simulation method A simulation apparatus capable of performing processing at a higher speed. The simulation apparatus is for VLIW processors, and includes a storage section for storing a program file which has a VLIW instruction formed of a predetermined instruction group, an instruction...	04/05/2007
20070067452	Mobile network dynamic workflow exception handling system Methods for using an exception handling system are provided for dynamically recovering from a workflow exception occurring in a healthcare mobile network communication system. An individual user can access the system through a hand-held mobile device. The system has mul...	03/22/2007
20070033382	Dynamic configuration of terminals for professional or customer usage A method of dynamically configuring a terminal within a business establishment can include comparing context information relating to terminal usage within the business establishment with context definitions specifying at least one of time-based rules or terminal usage p...	02/08/2007
20060206688	Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of...	09/14/2006
20060149925	High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel ...	07/06/2006
20060123218	System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which a...	06/08/2006
20060041736	Superscalar RISC instruction scheduling A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by...	02/23/2006
20050251653	System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The syste...	11/10/2005
20050102659	Methods and apparatus for setting up hardware loops in a deeply pipelined processor Methods and apparatus are provided for issuing instructions in a processor having a pipeline. A method includes providing a loop buffer for holding program loop instructions and a register file for holding loop control parameters; in response to decoding of a first loop...	05/12/2005
20050055538	Dynamic logic return-to-zero latching mechanism A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair o...	03/10/2005

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Class 712/23 - Superscalar