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| Application No. | Application Title | Issue Date |
| 20120110310 | MICROPROCESSOR WITH PIPELINE BUBBLE DETECTION DEVICE A microprocessor includes a pipeline microarchitecture and a pipeline bubble detection device. The pipeline bubble detection device has a minimum execution clock cycle ascertainment unit for ascertaining a minimum or optimum number of execution clock cycles for one or m... | 05/03/2012 |
| 20120084537 | SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION A filter executing on a processor monitors instructions executing on the processor to identify instructions that will benefit from performance tuning. Filtering instructions before analysis for performance tuning reduces overhead by identifying candidates for performanc... | 04/05/2012 |
| 20120084538 | Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state... | 04/05/2012 |
| 20120042153 | DATA PROCESSING SYSTEM HAVING TEMPORAL REDUNDANCY AND METHOD THEREFOR In a data processing system having execution circuitry, a method includes providing a reference instruction to the execution circuitry, the reference instruction having an operand; providing a cross-check instruction to the execution circuitry; executing the reference i... | 02/16/2012 |
| 20120023315 | Generating Hardware Events Via the Instruction Stream for Microprocessor Verification A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction th... | 01/26/2012 |
| 20110320783 | VERIFICATION USING OPCODE COMPARE A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to tr... | 12/29/2011 |
| 20110320784 | VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initializa... | 12/29/2011 |
| 20110314264 | Key allocation when tracing data processing systems A trace unit is provided which is configured to generate items of trace data indicative of processing activities, of a data processing unit. The trace unit comprises a trace indexing unit configured to associate an index value with at least a subset of the items of trac... | 12/22/2011 |
| 20110296147 | METHOD OF TESTING COMPUTER, COMPUTER TEST APPARATUS AND NON-TRANSITORY COMPUTER-READABLE MEDIUM A method of testing a computer, the method has designating a register as an input-only register having a setting of a value which does not cause an exception interruption with an execution of a specific type of instruction, generating a test instruction array having a p... | 12/01/2011 |
| 20110289301 | Tracing Flow of Data in a Distributed Computing Application A method is provided for tracing dataflow in a distributed computing application. For example, the method includes incrementally advancing a dataflow in a dataflow path of one or more dataflow paths according to two or more directives encoded in two or more data message... | 11/24/2011 |
| 20110289302 | DATA PROCESSING DEVICE AND METHOD Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a firs... | 11/24/2011 |
| 20110283094 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupl... | 11/17/2011 |
| 20110271085 | PARSING-ENHACEMENT FACILITY An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general ... | 11/03/2011 |
| 20110258421 | Architecture Support for Debugging Multithreaded Code Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attem... | 10/20/2011 |
| 20110225400 | Device for Testing a Multitasking Computation Architecture and Corresponding Test Method A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the se... | 09/15/2011 |
| 20110219216 | Mechanism for Performing Instruction Scheduling based on Register Pressure Sensitivity A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software ... | 09/08/2011 |
| 20110219217 | System on Chip Breakpoint Methodology A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing e... | 09/08/2011 |
| 20110185153 | SIMULTANEOUS EXECUTION RESUMPTION OF MULTIPLE PROCESSOR CORES AFTER CORE STATE INFORMATION DUMP TO FACILITATE DEBUGGING VIA MULTI-CORE PROCESSOR SIMULATOR USING THE STATE INFORMATION A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing us... | 07/28/2011 |
| 20110154122 | SYSTEM AND METHOD FOR OVERFLOW DETECTION USING SYMBOLIC ANALYSIS A method for demand-driven symbolic analysis involves obtaining a section of code comprising an instruction from a source code file and determining a critical variable in the section of code and data dependencies related to the critical variable. The method further invo... | 06/23/2011 |
| 20110154121 | CONCURRENCY TEST EFFICTIVENESS VIA MUTATION TESTING AND DYNAMIC LOCK ELISION One embodiment described herein is directed to a method practiced in a computing environment. The method includes acts for determining test suite effectiveness for testing for concurrency problems and/or product faults. The method includes identifying a plurality of syn... | 06/23/2011 |
| 20110138359 | MODIFIED IMPLEMENTATION OF JAVA DEBUG WIRE PROTOCOL A client debugger application or a virtual machine includes a receiving module configured to receive a command packet of a debugging protocol from a computer. The command packet includes an identifier (ID) field. The client debugger application or the virtual machine al... | 06/09/2011 |
| 20110131452 | Validation of Processors Using a Self-Generating Test Case Framework A method for testing processors is disclosed. The method includes generating a plurality of pools, where each pool includes a test program that includes a plurality of test cases, and setting a flag for each of the plurality of pools indicating that the pool is ready to... | 06/02/2011 |
| 20110131396 | TIMING ANALYSIS One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter v... | 06/02/2011 |
| 20110119528 | HARDWARE TRANSACTIONAL MEMORY ACCELERATION THROUGH MULTIPLE FAILURE RECOVERY The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactiona... | 05/19/2011 |
| 20110119651 | TECHNIQUES RELATED TO CUSTOMIZATIONS FOR COMPOSITE APPLICATIONS A framework is provided for enabling and managing customizations to an application. In one embodiment, techniques are provided that enable the customizability of an application to be controlled based upon hierarchical relations between elements of the application.... | 05/19/2011 |
| 20110113406 | SYMMETRIC MULTI-PROCESSOR LOCK TRACING A symmetric multi-processor SMP system includes an SMP processor and operating system OS software that performs automatic SMP lock tracing analysis on an executing application program. System administrators, users or other entities initiate an automatic SMP lock tracing... | 05/12/2011 |
| 20110078421 | ENHANCED MONITOR FACILITY A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, o... | 03/31/2011 |
| 20110047363 | Microprogrammable Device Code Tracing A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The system comprises binary code generating means, and a tracing device. The bin... | 02/24/2011 |
| 20110010531 | DEBUGGABLE MICROPROCESSOR A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The ... | 01/13/2011 |
| 20110010530 | MICROPROCESSOR WITH INTEROPERABILITY BETWEEN SERVICE PROCESSOR AND MICROCODE-BASED DEBUGGER A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external... | 01/13/2011 |
| 20100332808 | MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and tha... | 12/30/2010 |
| 20100325401 | Method of Translating N to N Instructions Employing an Enhanced Extended Translation Facility A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation... | 12/23/2010 |
| 20100325359 | TRACING OF DATA FLOW Embodiments for tracing dataflow for a computer program are described. The computer program includes machine instructions that are executable on a microprocessor. A decoding module can be configured to decode machine instructions obtained from a computer memory. In addi... | 12/23/2010 |
| 20100299507 | ON-LINE TESTING FOR DECODE LOGIC Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields... | 11/25/2010 |
| 20100287417 | ADDRESS TRANSLATION TRACE MESSAGE GENERATION FOR DEBUG A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug module generat... | 11/11/2010 |
| 20100281308 | TRACE MESSAGING DEVICE AND METHODS THEREOF A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable con... | 11/04/2010 |
| 20100268987 | Circuits And Methods For Processors With Multiple Redundancy Techniques For Mitigating Radiation Errors Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.... | 10/21/2010 |
| 20100262811 | DEBUG SIGNALING IN A MULTIPLE PROCESSOR DATA PROCESSING SYSTEM A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchron... | 10/14/2010 |
| 20100257343 | PROCESSING UNIT, DEVICE COMPRISING TWO PROCESSING UNITS, METHOD FOR TESTING A PROCESSING UNIT AND A DEVICE COMPRISING TWO PROCESSING UNITS A processing unit is described, comprising: a control unit adapted to execute after a reset phase a sequence of test instructions to detect a manipulation of the processing unit before the control unit decodes a first instruction for a normal operation.... | 10/07/2010 |
| 20100241899 | Debugging for multiple errors in a microprocessor environment A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is al... | 09/23/2010 |
