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| Application No. | Application Title | Issue Date |
| 20130086366 | Register File with Embedded Shift and Parallel Write Capability An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the register file receiving a register... | 04/04/2013 |
| 20130080740 | FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The executi... | 03/28/2013 |
| 20130024667 | ARITHMETIC AND CONTROL UNIT, ARITHMETHIC AND CONTROL METHOD, PROGRAM AND PARALLEL PROCESSOR An attribute group storage unit acquires and holds attribute groups set to respective data blocks. A scenario determination unit determines respective transfer systems of the respective blocks between a memory of the lowest hierarchy and a memory of another hierarchy ba... | 01/24/2013 |
| 20130024668 | ARCHITECTURE AND IMPLEMENTATION METHOD OF PROGRAMMABLE ARITHMETIC CONTROLLER FOR CRYPTOGRAPHIC APPLICATIONS An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (A... | 01/24/2013 |
| 20130013895 | BYTE-ORIENTED MICROCONTROLLER HAVING WIDER PROGRAM MEMORY BUS SUPPORTING MACRO INSTRUCTION EXECUTION, ACCESSING RETURN ADDRESS IN ONE CLOCK CYCLE, STORAGE ACCESSING OPERATION VIA POINTER COMBINATION, AND INCREASED POINTER ADJUSTMENT AMOUNT An exemplary byte-oriented microcontroller includes a program memory, a program memory bus, and a core circuit. The program memory bus has a bus width wider than one instruction byte, and the core circuit is coupled to the program memory through the program memory bus f... | 01/10/2013 |
| 20130007421 | Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication o... | 01/03/2013 |
| 20120311305 | INFORMATION PROCESSING DEVICE Provided is an information processing device including an instruction cache, a data cache, first and second arithmetic unit groups including a plurality of arithmetic units capable of parallel operation, a first arithmetic-control circuit that generates one or more oper... | 12/06/2012 |
| 20120260073 | EMULATION OF EXECUTION MODE BANKED REGISTERS A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions. A first set of storage elements holds a first subset of the operands and ... | 10/11/2012 |
| 20120254585 | METHOD AND APPARATUS FOR FAST BRANCH-FREE VECTOR DIVISION COMPUTATION Methods and apparatus for double precision division/inversion vector computations on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, an input argument is represented by an exponent portion and a fraction portion. These porti... | 10/04/2012 |
| 20120210101 | COMPETITION TESTING DEVICE A competition testing apparatus for testing an access competition of an arithmetic unit includes a memory that stores a program, a first processor that executes the program by accessing the memory, a second processor that executes the program by accessing the memory, an... | 08/16/2012 |
| 20120204012 | CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second in... | 08/09/2012 |
| 20120198212 | Microprocessor and Method for Enhanced Precision Sum-of-Products Calculation on a Microprocessor A microprocessor, a method for enhanced precision sum-of-products calculation and a video decoding device are provided, in which at least one general-purpose-register is arranged to provide a number of destination bits to a multiply unit, and a control unit is adapted t... | 08/02/2012 |
| 20120198211 | ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD FOR OPERATING WITH HIGHER AND LOWER CLOCK FREQUENCIES There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption u... | 08/02/2012 |
| 20120166773 | HASH PROCESSING USING A PROCESSOR In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i=1, ... | 06/28/2012 |
| 20120117441 | Processor Architecture for Executing Wide Transform Slice Instructions A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present inve... | 05/10/2012 |
| 20120083912 | ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively ... | 04/05/2012 |
| 20120079243 | Next-instruction-type-field A graphics processing unit core 26 includes a plurality of processing pipelines 38, 40, 42, 44. A program instruction of a thread of program instructions being executed by a processing pipeline includes a next-instruction-type field 36 indicating an... | 03/29/2012 |
| 20120079250 | FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function ... | 03/29/2012 |
| 20120079251 | MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruct... | 03/29/2012 |
| 20120072703 | SPLIT PATH MULTIPLY ACCUMULATE UNIT In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second pa... | 03/22/2012 |
| 20120060019 | REDUCTION OPERATION DEVICE, A PROCESSOR, AND A COMPUTER SYSTEM A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmis... | 03/08/2012 |
| 20120047354 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD According to one embodiment, an information processing apparatus includes: a first verification section configured to perform true-false determination for a predetermined verification target using a verification item obtained by combining specified one of plural verific... | 02/23/2012 |
| 20120030449 | DATA TAG CONTROL FOR QUANTUM-DOT CELLULAR AUTOMATA The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag... | 02/02/2012 |
| 20120023313 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias ... | 01/26/2012 |
| 20120017070 | COMPILE SYSTEM, COMPILE METHOD, AND STORAGE MEDIUM STORING COMPILE PROGRAM To provide a compile system, a compile method, and a compile program capable of improving the execution speed of a program. A compile system according to the present invention includes a primary arithmetic unit 030, a plurality of optimization arithmetic units 01/19/2012 | |
| 20110314263 | INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the s... | 12/22/2011 |
| 20110302393 | CONTROL SYSTEMS AND DATA PROCESSING METHOD When executing sequential processing such as a ladder logic, converting a program formed of an instruction set of another processor to a program executable by an own processor in software and then conducting processing lowers the real time property. In a control system,... | 12/08/2011 |
| 20110276790 | INSTRUCTION SUPPORT FOR PERFORMING MONTGOMERY MULTIPLICATION Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may incl... | 11/10/2011 |
| 20110271059 | REDUCING REMOTE READS OF MEMORY IN A HYBRID COMPUTING ENVIRONMENT A hybrid computing environment in which the host computer allocates, in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator; writes packet data to the accelerator's shared memory in a memory regi... | 11/03/2011 |
| 20110264896 | MICROPROCESSOR THAT FUSES MOV/ALU INSTRUCTIONS A microprocessor receives first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor. The first macroinstruction instructs the microprocessor to move a first operand to a first architectural register from a second archi... | 10/27/2011 |
| 20110246789 | INTEGRATED CIRCUIT PROTECTED AGAINST HORIZONTAL SIDE CHANNEL ANALYSIS An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of components xi of word x by components yj of word y is described. The multiplicat... | 10/06/2011 |
| 20110238958 | DATA PROCESSING DEVICE A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the... | 09/29/2011 |
| 20110238956 | Collective Acceleration Unit Tree Structure A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within... | 09/29/2011 |
| 20110238957 | SOFTWARE CONVERSION PROGRAM PRODUCT AND COMPUTER SYSTEM According to one embodiment, a software conversion program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer system including a host processor and one or more accelerator processors, causes... | 09/29/2011 |
| 20110208952 | PROGRAMMABLE CONTROLLER FOR EXECUTING A PLURALITY OF INDEPENDENT SEQUENCE PROGRAMS IN PARALLEL A programmable controller which executes a plurality of independent sequence programs in parallel is provided with an ASIC, including a plurality of arithmetic-logic units and a plurality of arbitration circuits, and MPUs as many as the arbitration circuits. The entire ... | 08/25/2011 |
| 20110208951 | INSTRUCTION PROCESSOR AND METHOD THEREFOR A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first acc... | 08/25/2011 |
| 20110191638 | PARALLEL COMPUTER SYSTEM AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM A parallel computer system includes a first, a second, and a third apparatuses. The first apparatus includes a first arithmetic processing unit that stores first information regarding execution of a first program stored in a first area of a first storage device in a sec... | 08/04/2011 |
| 20110161638 | Ising Systems: Helical Band Geometry For DTC and Integration of DTC Into A Universal Quantum Computational Protocol Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to implement a logical gate T, anyonic state teleportation into and out of the ... | 06/30/2011 |
| 20110153995 | ARITHMETIC APPARATUS INCLUDING MULTIPLICATION AND ACCUMULATION, AND DSP STRUCTURE AND FILTERING METHOD USING THE SAME Disclosed are an arithmetic apparatus including MAC calculation, and a DSP structure and a filtering method using the same. The arithmetic apparatus includes: first and second registers storing one or more pieces of n-bit data (n is a natural number); a third register s... | 06/23/2011 |
| 20110153994 | Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated b... | 06/23/2011 |
