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| Application No. | Application Title | Issue Date |
| 20120047352 | PROCESSOR A processor includes: an instruction buffer which stores the instructions to be dispatched to the arithmetic units; a dependency detecting unit which (i) detects a first dependency and a second dependency and (ii) determines an instruction group including the instructio... | 02/23/2012 |
| 20110320771 | INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is ... | 12/29/2011 |
| 20110302392 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determi... | 12/08/2011 |
| 20110276787 | MULTITHREAD PROCESSOR, COMPILER APPARATUS, AND OPERATING SYSTEM APPARATUS A multithread processor for executing, in parallel, instructions included in a plurality of threads includes: a calculating group including a plurality of calculators each of which is for executing an instruction; instruction grouping units which classify, for each thre... | 11/10/2011 |
| 20110231634 | SYSTEM AND METHOD FOR GROUPING ALTERNATIVE POSSIBILITIES IN AN UNKNOWN INSTRUCTION PATH A method, system and device is provided for processing digital data, for example, video, image, and media data. A dispatch unit may simultaneously issue a plurality of instructions to an execution unit. The instructions may correspond to different mutually exclusive out... | 09/22/2011 |
| 20110161623 | Data Parallel Function Call for Determining if Called Routine is Data Parallel Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate ... | 06/30/2011 |
| 20110138153 | MECHANISM FOR SELECTING INSTRUCTIONS FOR EXECUTION IN A MULTITHREADED PROCESSOR In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick fr... | 06/09/2011 |
| 20100312989 | Register renaming of a partially updated data granule A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction ... | 12/09/2010 |
| 20100257340 | System and Method for Group Formation with Multiple Taken Branches Per Group Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruc... | 10/07/2010 |
| 20100199072 | Register file A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request receive... | 08/05/2010 |
| 20100174884 | PROCESSOR HAVING RECONFIGURABLE ARITHMETIC ELEMENT A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable ... | 07/08/2010 |
| 20100138810 | PARALLELING PROCESSING METHOD, SYSTEM AND PROGRAM Paralleling processing system and method. When clusters are formed based on strongly connected components, a single cluster (fat cluster) having at least a predetermined number of blocks, or an expected processing time exceeding a predetermined threshold, is formed. The... | 06/03/2010 |
| 20100131741 | MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of ... | 05/27/2010 |
| 20100064121 | DUAL-ISSUANCE OF MICROPROCESSOR INSTRUCTIONS USING DUAL DEPENDENCY MATRICES A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruc... | 03/11/2010 |
| 20090228687 | PROCESSOR A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or not a... | 09/10/2009 |
| 20090217001 | System and Method for Handling Load and/or Store Operations in a Superscalar Microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to... | 08/27/2009 |
| 20090210656 | METHOD AND SYSTEM FOR OVERLAPPING EXECUTION OF INSTRUCTIONS THROUGH NON-UNIFORM EXECUTION PIPELINES IN AN IN-ORDER PROCESSOR A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also i... | 08/20/2009 |
| 20090210667 | System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a de... | 08/20/2009 |
| 20090210666 | System and Method for Resolving Issue Conflicts of Load Instructions The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a de... | 08/20/2009 |
| 20090210665 | System and Method for a Group Priority Issue Schema for a Cascaded Pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a de... | 08/20/2009 |
| 20090204792 | Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with r... | 08/13/2009 |
| 20090182987 | Processing Unit Incorporating Multirate Execution Unit A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the exec... | 07/16/2009 |
| 20090177868 | APPARATUS, SYSTEM, AND METHOD FOR DISCONTIGUOUS MULTIPLE ISSUE OF INSTRUCTIONS An apparatus, system, and method are disclosed for discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The plurality of issue units each comprises a renaming map that maps each archite... | 07/09/2009 |
| 20090172359 | PROCESSING PIPELINE HAVING PARALLEL DISPATCH AND METHOD THEREOF One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, ... | 07/02/2009 |
| 20090164758 | System and Method for Performing Locked Operations A mechanism for performing locked operations in a processing unit. A dispatch unit may dispatch a plurality of instructions including a locked instruction and a plurality of non-locked instructions. One or more of the non-locked instructions may be dispatched before and... | 06/25/2009 |
| 20090113181 | Method and Apparatus for Executing Instructions A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructi... | 04/30/2009 |
| 20090106534 | System and Method for Implementing a Software-Supported Thread Assist Mechanism for a Microprocessor A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch ... | 04/23/2009 |
| 20090089551 | Apparatus and method of avoiding bank conflict in single-port multi-bank memory system Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing ... | 04/02/2009 |
| 20090070559 | DATA PROCESSING CIRCUIT WHEREIN FUNCTIONAL UNITS SHARE READ PORTS A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled to... | 03/12/2009 |
| 20090049279 | THREAD INTERLEAVING IN A MULTITHREADED EMBEDDED PROCESSOR The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication laten... | 02/19/2009 |
| 20090031114 | MULTITHREAD PROCESSOR To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information... | 01/29/2009 |
| 20090006816 | Inter-Cluster Communication Network And Heirarchical Register Files For Clustered VLIW Processors A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster... | 01/01/2009 |
| 20080313433 | PROCESSOR FOR SIMULTANEOUSLY EXECUTING MULTIPLE CONDITIONAL EXECUTION INSTRUCTION GROUPS A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code b... | 12/18/2008 |
| 20080288745 | GENERATING PREDICATE VALUES DURING VECTOR PROCESSING A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses ... | 11/20/2008 |
| 20080263330 | Clocked ports A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between... | 10/23/2008 |
| 20080222336 | DATA PROCESSING SYSTEM To allow to use arithmetic circuits of sharable resources by priority with a simple procedure. In a data processing system including central processing units and a plurality of arithmetic circuits, wherein the central processing units are able to supply a command to one... | 09/11/2008 |
| 20080195846 | Distributed Dispatch with Concurrent, Out-of-Order Dispatch In one embodiment, a processor comprises an instruction buffer and a pick unit. The instruction buffer is coupled to receive instructions fetched from an instruction cache. The pick unit is configured to select up to N instructions from the instruction buffer for concur... | 08/14/2008 |
| 20080155496 | PROGRAM FOR PROCESSOR CONTAINING PROCESSOR ELEMENTS, PROGRAM GENERATION METHOD AND DEVICE FOR GENERATING THE PROGRAM, PROGRAM EXECUTION DEVICE, AND RECORDING MEDIUM A program for execution by a computer that includes a plurality of processor elements, the program comprising: a parallel execution program part to assign the plurality of processor elements one-to-one to a plurality of program parts so that the plurality of program par... | 06/26/2008 |
| 20080133890 | DYNAMIC RECALCULATION OF RESOURCE VECTOR AT ISSUE QUEUE FOR STEERING OF DEPENDENT INSTRUCTIONS A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions... | 06/05/2008 |
| 20080104372 | METHOD, APPARATUS AND COMPUTER PROGRAM FOR EXECUTING A PROGRAM There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined typi... | 05/01/2008 |
