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| Application No. | Application Title | Issue Date |
| 20120072700 | MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level regis... | 03/22/2012 |
| 20120023314 | PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is d... | 01/26/2012 |
| 20110320771 | INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is ... | 12/29/2011 |
| 20110314260 | HIGH-WORD FACILITY FOR EXTENDING THE NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small G... | 12/22/2011 |
| 20110296142 | PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS THAT UTILIZE MULTIPLE REGISTER WINDOWS A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction exec... | 12/01/2011 |
| 20110296143 | PIPELINE PROCESSOR AND AN EQUAL MODEL CONSERVATION METHOD A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of s... | 12/01/2011 |
| 20110276784 | HIERARCHICAL MULTITHREADED PROCESSING In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads ... | 11/10/2011 |
| 20110252220 | INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction i... | 10/13/2011 |
| 20110246995 | CACHE-AWARE THREAD SCHEDULING IN MULTI-THREADED SYSTEMS The disclosed embodiments provide a system that facilitates scheduling threads in a multi-threaded processor with multiple processor cores. During operation, the system executes a first thread in a processor core that is associated with a shared cache. During this execu... | 10/06/2011 |
| 20110225398 | ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging ne... | 09/15/2011 |
| 20110208950 | PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a sou... | 08/25/2011 |
| 20110153991 | DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit opera... | 06/23/2011 |
| 20110153989 | SYNCHRONIZING SIMD VECTORS A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, a... | 06/23/2011 |
| 20110138152 | INSTRUCTION CONTROL DEVICE A processor which executes threads having different characteristics is provided with an instruction control device. In the instruction control device, a first instruction control unit issues an instruction included in a first instruction sequence to an instruction execu... | 06/09/2011 |
| 20110099354 | Information processing apparatus and instruction decoder for the information processing apparatus An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of in... | 04/28/2011 |
| 20110078416 | APPARATUS AND METHOD FOR CONTROL PROCESSING IN DUAL PATH PROCESSOR A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units... | 03/31/2011 |
| 20110078414 | MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions s... | 03/31/2011 |
| 20110072243 | Unified Collector Structure for Multi-Bank Register File One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by ... | 03/24/2011 |
| 20110072244 | Credit-Based Streaming Multiprocessor Warp Scheduling One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by ... | 03/24/2011 |
| 20110055523 | EARLY BRANCH DETERMINATION A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method fur... | 03/03/2011 |
| 20110004743 | Pipe scheduling for pipelines based on destination register number A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process instructions. At least one instruction includ... | 01/06/2011 |
| 20100332804 | UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information r... | 12/30/2010 |
| 20100325394 | System and Method for Balancing Instruction Loads Between Multiple Execution Units Using Assignment History A system and method for balancing instruction loads between multiple execution units are disclosed. One or more execution units may be represented by a slot configured to accept instructions on behalf of the execution unit(s). A decode unit may assign instructions to a ... | 12/23/2010 |
| 20100318769 | USING VECTOR ATOMIC MEMORY OPERATION TO HANDLE DATA OF DIFFERENT LENGTHS A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number ... | 12/16/2010 |
| 20100312992 | MULTITHREAD EXECUTION DEVICE AND METHOD FOR EXECUTING MULTIPLE THREADS A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution... | 12/09/2010 |
| 20100306505 | Result path sharing between a plurality of execution units within a processor A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines fu... | 12/02/2010 |
| 20100306504 | Controlling issue and execution of instructions having multiple outcomes At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one ope... | 12/02/2010 |
| 20100299504 | MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the pluralit... | 11/25/2010 |
| 20100262808 | MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining... | 10/14/2010 |
| 20100257339 | Dependency Matrix with Improved Performance A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell in the first array represents a dep... | 10/07/2010 |
| 20100257341 | Selective Execution Dependency Matrix A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationshi... | 10/07/2010 |
| 20100257336 | Dependency Matrix with Reduced Area and Power Consumption A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to th... | 10/07/2010 |
| 20100246815 | APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE KASUMI CIPHER ALGORITHM A processor including instruction support for implementing the Kasumi block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive i... | 09/30/2010 |
| 20100228955 | METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine loca... | 09/09/2010 |
| 20100205406 | OUT-OF-ORDER EXECUTION MICROPROCESSOR THAT SPECULATIVELY EXECUTES DEPENDENT MEMORY ACCESS INSTRUCTIONS BY PREDICTING NO VALUE CHANGE BY OLDER INSTRUCTIONS THAT LOAD A SEGMENT REGISTER An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register of the microprocessor. A comparator compares the new value specified by t... | 08/12/2010 |
| 20100131740 | DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD The workload is heavy in the development of an application program that controls the task distribution in consideration of the variety of the execution environment. In a system where the processing is distributed to SPUs serving as plural processing entities so as to ex... | 05/27/2010 |
| 20100122067 | ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The d... | 05/13/2010 |
| 20100106945 | Instruction processing apparatus The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective... | 04/29/2010 |
| 20100100712 | Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic i... | 04/22/2010 |
| 20100082947 | VERY-LONG INSTRUCTION WORD ARCHITECTURE WITH MULTIPLE PROCESSING UNITS A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instruct... | 04/01/2010 |
