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| Application No. | Application Title | Issue Date |
| 20110302390 | SYSTEMS AND METHODS FOR PROCESSING COMMUNICATIONS SIGNALS fUSING PARALLEL PROCESSING Systems and methods for performing processing of communications signals on multi-processor architectures. The system consists of a digital interface that translate numbers that represent a waveform in some format to analog signals for use in transmission and translating... | 12/08/2011 |
| 20110055516 | Multiprocessor Computer System and Method Having at Least One Processor with a Dynamically Reconfigurable Instruction Set An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement ... | 03/03/2011 |
| 20100293534 | USE OF VECTORIZATION INSTRUCTION SETS In one embodiment, the invention is a method and apparatus for use of vectorization instruction sets. One embodiment of a method for generating vector instructions includes receiving source code written in a high-level programming language, wherein the source code inclu... | 11/18/2010 |
| 20100281234 | INTERLEAVED MULTI-THREADED VECTOR PROCESSOR A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of regist... | 11/04/2010 |
| 20100095086 | Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality o... | 04/15/2010 |
| 20100088473 | VECTOR COMPUTER SYSTEM WITH CACHE MEMORY AND OPERATION METHOD THEREOF A vector computer system includes a vector processor configured to issue a vector store instruction which includes a plurality of store requests; a cache memory of a write back system provided between the vector processor and a main memory; and a write allocate determin... | 04/08/2010 |
| 20100042807 | INCREMENT-PROPAGATE AND DECREMENT-PROPAGATE INSTRUCTIONS FOR PROCESSING VECTORS The described embodiments provide a processor for generating a result vector with incremented or decremented values from an input vector. During operation, the processor receives an input vector and a control vector. The processor then copies a value contained in a sele... | 02/18/2010 |
| 20090172348 | METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA A computer processor includes control logic for executing LoadUnpack and PackStore instructions. In one embodiment, the processor includes a vector register and a mask register. In response to a PackStore instruction with an argument specifying a memory location, a circ... | 07/02/2009 |
| 20090150647 | Processing Unit Incorporating Vectorizable Execution Unit A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical execution units in different modes. By doing so, processing lanes can be selec... | 06/11/2009 |
| 20090144521 | METHOD AND APPARATUS FOR SEARCHING EXTENSIBLE MARKUP LANGUAGE (XML) DATA Extensible Markup Language (XML) data is represented as a list of structures with each structure in the list representing an aspect of the XML. A set of frequently used elements is extracted from the list of structure representation and stored in packed vectors. The pac... | 06/04/2009 |
| 20090106525 | DESIGN STRUCTURE FOR SCALAR PRECISION FLOAT IMPLEMENTATION ON THE "W" LANE OF VECTOR UNIT A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for image processing, and more specifically to vector units for supporting image processing is provided. A combined vector/scalar unit is provided wher... | 04/23/2009 |
| 20080114964 | Apparatus and Method for Cache Maintenance A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the c... | 05/15/2008 |
| 20080082783 | Dual Independent and Shared Resource Vector Execution Units with Shared Register File The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implem... | 04/03/2008 |
| 20080052489 | Multi-Pipe Vector Block Matching Operations A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes pr... | 02/28/2008 |
| 20070150697 | Vector processor with multi-pipe vector block matching A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes pr... | 06/28/2007 |
| 20070143575 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to... | 06/21/2007 |
| 20070143574 | Method and apparatus for supporting vector operations on a multi-threaded microprocessor One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the ... | 06/21/2007 |
| 20070136559 | METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transf... | 06/14/2007 |
| 20070061550 | INSTRUCTION EXECUTION IN A PROCESSOR A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of valu... | 03/15/2007 |
| 20070038842 | Data recording processor and method for use in an active memory device An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, whi... | 02/15/2007 |
| 20060155925 | Data access in a processor A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying ... | 07/13/2006 |
| 20060149920 | Object oriented mission framework and system and method A mission system includes a peer vector machine having a host processor and pipeline accelerator and including bridge objects that provide communication via signal objects, message objects, and mission objects. ... | 07/06/2006 |
| 20060136700 | Vector processing system A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing un... | 06/22/2006 |
| 20060020768 | Vector processing apparatus, Information processing apparatus, and vector processing method A vector processing apparatus includes a plurality of vector pipeline computing units and an instruction control unit. The vector pipeline computing units operate in accordance with operation control information for instructing start and execution of processing. The ins... | 01/26/2006 |
| 20060004985 | Vector SIMD processor A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An opera... | 01/05/2006 |
| 20050251644 | Physics processing unit instruction set architecture An efficient quasi-custom instruction set for Physics Processing Unit (PPU) is enabled by balancing the dictates of a parallel arrangement of multiple, independent vector processors and programming considerations. A hierarchy of multiple, programmable memories and distr... | 11/10/2005 |
| 20050251645 | Method and apparatus for staggering execution of an instruction A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logica... | 11/10/2005 |
| 20050228846 | Magnitude comparator A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compa... | 10/13/2005 |
| 20050188178 | Vector processing apparatus with overtaking function A vector processing apparatus includes a main memory, an instruction issuing section, an overtaking control circuit and an instruction executing section. The instruction issuing section sequentially issues instructions. A first instruction of the instructions is issued,... | 08/25/2005 |
| 20050172101 | Secured inter-processor and virtual device communications system The invention comprises an electronically secured inter-processor and virtual device communications system, with an input/output controller board, a multi-drop bus interface to multiple devices, and a parallel interface to an industry standard single board computer. The... | 08/04/2005 |
| 20050102487 | Vector processor with data swap and replication A microprocessor includes a branch unit, a load/store unit (LSU), an arithmetic logic unit (ALU), and a vector unit to execute a vector instruction. The vector unit includes a vector register file having a primary vector register and a secondary vector register. The pro... | 05/12/2005 |
| 20050097299 | Processor with asymmetric SIMD functionality A microprocessor including an execution unit enabled to execute an asymmetric instruction, where the asymmetric instruction includes a set of operand fields and an operation code (opcode). The execution unit is configured to interpret the opcode to perform a first opera... | 05/05/2005 |
