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| Application No. | Application Title | Issue Date |
| 20120047349 | DATA TRANSFER SYSTEM A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to other processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arb... | 02/23/2012 |
| 20110314256 | Data Parallel Programming Model Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expr... | 12/22/2011 |
| 20110153981 | Heterogeneous computer architecture based on partial reconfiguration Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically intercon... | 06/23/2011 |
| 20100281236 | APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A VECTOR PROCESSOR An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the... | 11/04/2010 |
| 20100241758 | SYSTEM AND METHOD FOR HARDWARE ACCELERATED MULTI-CHANNEL DISTRIBUTED CONTENT-BASED DATA ROUTING AND FILTERING Systems and methods for hardware accelerated multi-channel content-based data routing and filter. Data packets are received at a filtering circuit from one or more sources. The packets are filtered in accordance with parameters established by a system user to select spe... | 09/23/2010 |
| 20100235608 | METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is ... | 09/16/2010 |
| 20100138633 | Variable clocked heterogeneous serial array processor A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at ... | 06/03/2010 |
| 20100066748 | Method And Apparatus For Scheduling The Processing Of Multimedia Data In Parallel Processing Systems An efficient method and device for the parallel processing of multimedia data. Blocks (or portions thereof) are transmitted to various parallel processors, in the order of their dependency data. Earlier blocks are sent to the parallel processors first, with later blocks... | 03/18/2010 |
| 20090319755 | Method and Apparatus for High Speed Data Stream Splitter on an Array of Processors A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors 305(da), which splits off a substream and passes the d... | 12/24/2009 |
| 20090300324 | ARRAY TYPE PROCESSOR AND DATA PROCESSING SYSTEM In data path means, processor elements individually execute data processing in accordance with command codes described in a computer program, and switching elements individually control a connection relationship to switch among a plurality of processor elements in accor... | 12/03/2009 |
| 20090113170 | Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and de... | 04/30/2009 |
| 20080126746 | NETWORK OF SINGLE-WORD PROCESSORS FOR SEARCHING PREDEFINED DATA IN TRANSMISSION PACKETS AND DATABASES The present invention related to monitoring internet traffic for illegal Intellectual Property transfers, viruses, criminal and other illegal activities. It also assists the Internet search engine providers in generating fast and accurate responses to Internet Recipient... | 05/29/2008 |
| 20080082787 | Delay circuit and processor A delay circuit that can prevent an increase in the scale of circuits. A data delay section included in the delay circuit delays input data by a plurality of data delay elements. A validity information delay section included in the delay circuit delays input validity in... | 04/03/2008 |
| 20080034184 | FAULT TOLERANT CELL ARRAY ARCHITECTURE A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the... | 02/07/2008 |
| 20070245122 | Executing an Allgather Operation on a Parallel Computer Executing an allgather operation on a parallel computer that includes a plurality of compute nodes where the compute nodes are organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer, and each compute no... | 10/18/2007 |
| 20050273310 | Enhancements to performance monitoring architecture for critical path-based analysis A method and apparatus is described herein for monitoring the performance of a microarchitecture and tuning the microarchitecture based on the monitored performance. Performance is monitored through simulation, analytical reasoning, retirement pushout measure, overall e... | 12/08/2005 |
| 20050120190 | Hardware assisted communication between processors A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor ... | 06/02/2005 |
| 20050091472 | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plur... | 04/28/2005 |
