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| Application No. | Application Title | Issue Date |
| 20110264888 | Dynamically Reconfigurable Systolic Array Accelorators A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and ha... | 10/27/2011 |
| 20110238948 | METHOD AND DEVICE FOR COUPLING A DATA PROCESSING UNIT AND A DATA PROCESSING ARRAY The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and a... | 09/29/2011 |
| 20110153981 | Heterogeneous computer architecture based on partial reconfiguration Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically intercon... | 06/23/2011 |
| 20100293356 | METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plur... | 11/18/2010 |
| 20100281235 | RECONFIGURABLE FLOATING-POINT AND BIT-LEVEL DATA PROCESSING UNIT Blocks of fixed-point units in a reconfigurable data processing unit assist the efficient calculation of floating decimal point numbers by virtue of joint hardware functions permanently implemented within the block.... | 11/04/2010 |
| 20100268911 | Method and Apparatus for Dynamic Partial Reconfiguration on an Array of Processors A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the n... | 10/21/2010 |
| 20100268862 | RECONFIGURABLE PROCESSOR AND METHOD OF RECONFIGURING THE SAME A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration da... | 10/21/2010 |
| 20100257335 | RECONFIGURABLE CIRCUIT WITH SUSPENSION CONTROL CIRCUIT A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit config... | 10/07/2010 |
| 20100228925 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SHARED MEMORY OF COMMUNICATION ELEMENTS A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of process... | 09/09/2010 |
| 20100228918 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.... | 09/09/2010 |
| 20100211747 | PROCESSOR WITH RECONFIGURABLE ARCHITECTURE Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory... | 08/19/2010 |
| 20100199068 | RECONFIGURABLE PROCESSOR FOR REDUCED POWER CONSUMPTION AND METHOD THEREOF Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a di... | 08/05/2010 |
| 20100174884 | PROCESSOR HAVING RECONFIGURABLE ARITHMETIC ELEMENT A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable ... | 07/08/2010 |
| 20100174885 | RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory ... | 07/08/2010 |
| 20100042871 | System with Configurable Functional Units and Method A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of... | 02/18/2010 |
| 20090327653 | RECONFIGURABLE COMPUTING CIRCUIT A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers ... | 12/31/2009 |
| 20090319754 | Reconfigurable device A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from ... | 12/24/2009 |
| 20090282213 | SEMICONDUCTOR INTEGRATED CIRCUIT A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in confi... | 11/12/2009 |
| 20090249028 | PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS The present invention relates to a processor that, as its main feature, has an internal raster of ALUs, with the help of which sequential programs are executed. The connections between the ALUs are automatically created at runtime dynamically by means of multiplexers. A... | 10/01/2009 |
| 20090187733 | Virtual Configuration Management for Effiicient Use of Reconfigurable Hardwware Reconfigurable Computers (RCs) can leverage the synergism between conventional processors and FPGAs by combining the flexibility of traditional microprocessors with the parallelism of hardware and reconfigurability of FPGAs. Multiple challenges must be resolved to devel... | 07/23/2009 |
| 20090172351 | DATA PROCESSING DEVICE AND METHOD A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock ra... | 07/02/2009 |
| 20090144522 | Data Processing Device and Method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock ra... | 06/04/2009 |
| 20090119480 | Method, System and Program for Developing and Scheduling Adaptive Integrated Circuitry and Corresponding Control or Configuration Information A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exempla... | 05/07/2009 |
| 20090113169 | RECONFIGURABLE ARRAY PROCESSOR FOR FLOATING-POINT OPERATIONS A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the recei... | 04/30/2009 |
| 20090070550 | Operational dynamics of three dimensional intelligent system on a chip The invention pertains to a 3D intelligent SoC. The self-regulating data flow mechanisms of the 3D SoC are elucidated, particularly parallelization of multiple asynchronous 3D IC nodes and reconfigurable components. These behavioral mechanisms are organized into a polym... | 03/12/2009 |
| 20090037693 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plur... | 02/05/2009 |
| 20090037691 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plur... | 02/05/2009 |
| 20090037692 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plur... | 02/05/2009 |
| 20080294870 | SWITCH MEMORY ARCHITECTURES The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE), (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between two ... | 11/27/2008 |
| 20080250225 | SEMICONDUCTOR DEVICE HAVING MATRIX OF PROCESSING MODULES INTERCONNECTED BY LOCAL AND GLOBAL SELF-SYNCHRONOUS BUSES A semiconductor device includes a plurality of processing clusters that operate synchronously internally and arranged in a M×N matrix. Each processing cluster is formed as a plurality of processing elements and clocked buses that interconnect the processing elements wi... | 10/09/2008 |
| 20080235490 | SYSTEM FOR CONFIGURING A PROCESSOR ARRAY Embodiments of the invention are directed to a system for configuring a processor array using configuration chains streamed down communication channels.... | 09/25/2008 |
| 20080082786 | Super-scalable, continuous flow instant logic™ binary circuitry actively structured by code-generated pass transistor interconnects A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/vo... | 04/03/2008 |
| 20080010437 | Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS) An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration... | 01/10/2008 |
| 20070204131 | MULTI-ADAPTIVE PROCESSING SYSTEMS AND TECHNIQUES FOR ENHANCING PARALLELISM AND PERFORMANCE OF COMPUTATIONAL FUNCTIONS Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algor... | 08/30/2007 |
| 20070118721 | APPARATUS FOR CONTROLLING ACCESS IN A DATA PROCESSOR A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part for ... | 05/24/2007 |
| 20070113046 | Data processing device and method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock ra... | 05/17/2007 |
| 20070083733 | Reconfigurable circuit and control method therefor A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration informa... | 04/12/2007 |
| 20070074001 | Reconfigurable integrated circuit device A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which ... | 03/29/2007 |
| 20070042210 | Mesh and methods and apparatus for forming and using mesh A method of forming a mesh by a moulding a link element around other link elements to form a mesh in which the interlinking link elements are formed as continuous unjoined loops by a moulding process. An apparatus for forming a mesh including a plurality of first caviti... | 02/22/2007 |
| 20070011435 | Mesh node association method in a mesh network, and mesh network supporting the same A mesh network has a plurality of mesh nodes, including a moving mesh node. A serving mesh node initially associates with the moving mesh node at the request of the moving mesh node, transmits context information due to the initial association to at least one neighbor m... | 01/11/2007 |
