Bizarre Patents
Smoking Cessation Lighter and Method
A lighter for tobacco products suppresses the urge to smoke by operant conditioning.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120017066 | LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE Data processing device comprising a multidimensional array of ALUs, having at least two dimension where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresp... | 01/19/2012 |
| 20110219208 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technolog... | 09/08/2011 |
| 20110213946 | PARALLEL COMPUTING SYSTEM AND COMMUNICATION CONTROL PROGRAM A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in th... | 09/01/2011 |
| 20110173413 | EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodimen... | 07/14/2011 |
| 20110161625 | Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each dimension of a G×H matrix of nodes, where G≧N and H≧N and N is a positive od... | 06/30/2011 |
| 20110153936 | Aggregate Symmetric Multiprocessor System An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second... | 06/23/2011 |
| 20110145544 | MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to f... | 06/16/2011 |
| 20110072237 | Methods and apparatus for efficiently sharing memory and processing in a multi-processor A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any s... | 03/24/2011 |
| 20100287318 | I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be c... | 11/11/2010 |
| 20100274975 | Forming Multiprocessor Systems Using Dual Processors In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the M... | 10/28/2010 |
| 20100229020 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SELECTIVE DATA TRANSFER THROUGH COMMUNICATON ELEMENTS A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of process... | 09/09/2010 |
| 20100191911 | System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupl... | 07/29/2010 |
| 20100174883 | PROCESSOR ARCHITECTURES FOR ENHANCED COMPUTATIONAL CAPABILITY AND LOW LATENCY A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute... | 07/08/2010 |
| 20100169896 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING A COMMUNICATION An electronic device is provided which comprises a plurality of processing units (IP; IP1-IP4), an interconnect (IPCU; N) for coupling the processing units (IP; IP1-IP4) to enable a communication between the processing units (IP; IP1-I... | 07/01/2010 |
| 20100158076 | Direct Sequence Spread Spectrum Correlation Method for a Multiprocessor Array A method and apparatus for correlation of a received DSSS signal with a PN sequence, thus significantly reducing the processing time and operating power needed to acquire phase information for DSSS de-spreading and demodulation. The apparatus utilizes a multiprocessor a... | 06/24/2010 |
| 20100100703 | System For Parallel Computing A system and a method for parallel computing for solving complex problems is envisaged. Particularly, hierarchical parallel computing system is envisaged by this invention, which is formed by multiple levels of groups, where each group consists of multiple processing el... | 04/22/2010 |
| 20100082863 | I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be c... | 04/01/2010 |
| 20090193225 | SYSTEM AND METHOD FOR APPLICATION SPECIFIC ARRAY PROCESSING A processing architecture and methods therein for building application specific array processing utilizing a sequential data bus for control and data propagation. The methods of array processing provided by the architecture allows for numerical analysis of large numeric... | 07/30/2009 |
| 20090158007 | SCALEABLE ARRAY OF MICRO-ENGINES FOR WAVEFORM PROCESSING A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to ... | 06/18/2009 |
| 20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus ele... | 06/11/2009 |
| 20090144522 | Data Processing Device and Method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock ra... | 06/04/2009 |
| 20090094436 | ULTRA-SCALABLE SUPERCOMPUTER BASED ON MPU ARCHITECTURE The invention provides an ultra-scalable supercomputer based on MPU architecture in achieving the well-balanced performance of hundreds of TFLOPS or PFLOPS range in applications. The supercomputer system design includes the interconnect topology and its corresponding ro... | 04/09/2009 |
| 20090055624 | CONTROL OF PROCESSING ELEMENTS IN PARALLEL PROCESSORS The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the ar... | 02/26/2009 |
| 20080244221 | EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to p... | 10/02/2008 |
| 20080209163 | DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing syste... | 08/28/2008 |
| 20080195842 | ARRAY-TYPE PROCESSOR Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception b... | 08/14/2008 |
| 20080176750 | SYSTEMS, DEVICES, AND METHODS FOR INTERCONNECTED PROCESSOR TOPOLOGY An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may pro... | 07/24/2008 |
| 20080162872 | DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING HIGH BANDWIDTH COMMUNICATION BETWEEN NODES A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second proces... | 07/03/2008 |
| 20080148120 | Storing multicore chip test data An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test ... | 06/19/2008 |
| 20080148009 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATION ELEMENTS A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of process... | 06/19/2008 |
| 20080133879 | SIMD parallel processor with SIMD/SISD/row/column operation modes Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register ... | 06/05/2008 |
| 20080109635 | GENERAL PURPOSE ARRAY PROCESSING General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and opera... | 05/08/2008 |
| 20080104367 | Collective Network For Computer Structures A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executin... | 05/01/2008 |
| 20080059761 | FAULT TOLERANT CELL ARRAY ARCHITECTURE A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the... | 03/06/2008 |
| 20080059762 | Multi-sequence control for a data parallel system The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is... | 03/06/2008 |
| 20080052491 | Manifold Array Processor An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually... | 02/28/2008 |
| 20080052490 | Computational resource array A sea of computational resources includes a number of computational resources, each of which is a member of one or more nearest neighbor pairings. Each nearest neighbor pairing has an upstream neighbor and a downstream neighbor, and each nearest neighbor pairing transfe... | 02/28/2008 |
| 20080010436 | PARALLEL DATA PROCESSING APPARATUS A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing el... | 01/10/2008 |
| 20070294508 | Parallel pseudorandom number generation A method of generating pseudo-random numbers on a parallel processing system comprises generating a plurality of sub-streams of pseudo-random numbers, wherein the sub-streams are generated in parallel by one or more co-processors, and providing the plurality of sub-stre... | 12/20/2007 |
| 20070260847 | Reconfigurable integrated circuit A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one o... | 11/08/2007 |
