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| Application No. | Application Title | Issue Date |
| 20100325386 | PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruc... | 12/23/2010 |
| 20100318765 | ACTIVE MEMORY COMMAND ENGINE AND METHOD A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also gener... | 12/16/2010 |
| 20100281234 | INTERLEAVED MULTI-THREADED VECTOR PROCESSOR A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of regist... | 11/04/2010 |
| 20100174868 | Processor device having a sequential data processing unit and an arrangement of data processing elements Designing a coupling of a traditional processor, in particular a sequential processor, and a reconfigurable field of data processing units, in particular a runtime-reconfigurable field of data processing units is described.... | 07/08/2010 |
| 20100115235 | Eliminating Synchronous Grace Period Detection For Non-Preemptible Read-Copy Update On Uniprocessor Systems A technique for optimizing grace period detection in a uniprocessor environment. An update operation is performed on a data element that is shared with non-preemptible readers of the data element. A call is issued to a synchronous grace period detection method. The sync... | 05/06/2010 |
| 20090259824 | RECONFIGURABLE INTEGRATED CIRCUIT A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements... | 10/15/2009 |
| 20090119479 | INTEGRATED CIRCUIT ARRANGEMENT FOR CARRYING OUT BLOCK AND LINE BASED PROCESSING OF IMAGE DATA An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are ... | 05/07/2009 |
| 20090070549 | Interconnect architecture in three dimensional network on a chip The connection architecture of a network on a chip (NoC) is described in which (a) nodes in octahedron sections are connected in an arc Benes network, (b) a hierarchy of node clusters are connected using a globally asynchronous locally asynchronous (GALA) configuration,... | 03/12/2009 |
| 20090063811 | System for Data Processing Using a Multi-Tiered Full-Graph Interconnect Architecture A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plura... | 03/05/2009 |
| 20080307194 | Parallel, Low-Latency Method for High-Performance Deterministic Element Extraction From Distributed Arrays The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a local array with elements from input, a module that submits a largest element value in the l... | 12/11/2008 |
| 20080104366 | Semiconductor chip Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace a... | 05/01/2008 |
| 20080010435 | MEMORY SYSTEMS AND MEMORY MODULES One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a... | 01/10/2008 |
| 20070300041 | Method for processing streaming data in a multiprocessor system The present invention relates to a method for processing streaming data in a multiprocessor system. In this method, in a pipelining architecture of the multiprocessor system a specified number of processors having a specified number of programs processes, in a clocked m... | 12/27/2007 |
| 20070294507 | ASYMMETRIC CLUSTERED PROCESSOR ARCHITECTURE BASED ON VALUE CONTENT A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a clu... | 12/20/2007 |
| 20070266223 | Network-on-Chip Dataflow Architecture With the development of microelectronic industry, we can integrate more and more transistors in a single chip. According to Moore's law, the number of transistors can double in 18 months. Therefore, our target is how to convert the number of transistors to the performan... | 11/15/2007 |
| 20070245120 | Multiple microcontroller system, instruction, and instruction execution method for the same In a multiple microcontroller system comprising multiple MCU core logics, a multiple-MCU-core-logic selection operand is provided in an instruction according to this invention. The multiple-MCU-core-logic selection operand specifies or selects a corresponding MCU core l... | 10/18/2007 |
| 20070226455 | Variable clocked heterogeneous serial array processor A serial array processor, whose execution unit, which s comprised of a multiplicity of single bit arithmetic logic units (ALUs), performs parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while the i... | 09/27/2007 |
| 20070226457 | Computer system with increased operating efficiency A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor.... | 09/27/2007 |
| 20070226456 | System and method for employing multiple processors in a computer system There is provided a system and a method for employing multiple processors in a computer system. More specifically, there is provided a computer system comprising a first cell board including a first central processing unit, a second central processing unit, and a first ... | 09/27/2007 |
| 20070226454 | Highly scalable MIMD machine for java and .net processing An MIMD processor for Java and Net processing includes a plurality of “half-processors,” separate execution units, and memory caches. Each half-processor is an MIMD processing element having resources for instruction fetch and decode and for instruction stream conte... | 09/27/2007 |
| 20070186078 | Integrated Circuit Device An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data... | 08/09/2007 |
| 20070162722 | Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems An efficient method and device for the parallel processing of data variables. A parallel processing array has computing elements configured to process data variables in parallel. An algorithm for a plurality of computing elements of a parallel processor is loaded. The a... | 07/12/2007 |
| 20070143576 | Apparatus and method for performing signal processing A system for performing signal processing includes a system input, wherein a first signal having a first format, and supplied on a first system input is selected by a user for format conversion. A switching circuit having plural switching circuit inputs and plural switc... | 06/21/2007 |
| 20070143577 | RECONFIGURABLE INTEGRATED CIRCUIT A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements... | 06/21/2007 |
| 20070136559 | METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transf... | 06/14/2007 |
| 20070130444 | Integrated processor array, instruction sequencer and I/O controller A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. Th... | 06/07/2007 |
| 20070124561 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also gener... | 05/31/2007 |
| 20070083730 | Data processing device and method The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and a... | 04/12/2007 |
| 20070067605 | Architecture of a parallel-processing multi-microcontroller system and timing control method thereof The present invention discloses the architecture of a parallel-processing multi-microcontroller system and a timing control method thereof. The multi-microcontroller system of the present invention comprises multiple microcontroller program execution status modules, and... | 03/22/2007 |
| 20070067606 | Heterogeneous parallel processing based on processor performance In at least some embodiments, a system, comprises a first computing unit having a first type of processors. The system further comprises a second computing unit having a second type of processors, the second computing unit being coupled to the first computing unit. The ... | 03/22/2007 |
| 20070033379 | Active memory processing array topography and method An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical ro... | 02/08/2007 |
| 20060282647 | Parallel processing system The invention is based on the idea to provide a functional unit that is capable of performing not only a simple pass operation but also delayed pass operations, introducing a desired amount of latency. Therefore, a parallel processor is provided, wherein said processor ... | 12/14/2006 |
| 20060265569 | Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor The present invention provides a processor capable of carrying out a plurality of operation instructions simultaneously in one cycle which improves utilization of an instruction when carrying out a single operation instruction, and a system equipped with such a processo... | 11/23/2006 |
| 20060218375 | System and method of transferring data between a massive number of processors This present invention brings to the multiprocessor what vectorization brought to the single processor. It provides similar tools to speed communication that have traditionally been used to speed computation; namely, the capability to program optimal communication algor... | 09/28/2006 |
| 20060195663 | Virtualized I/O adapter for a multi-processor data processing system An enhanced SCSI storage adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the operating system (OS) owns the SCSI storage adapter, controls the adapter queues, both creation of and changes to the queues, an... | 08/31/2006 |
| 20060155969 | Reconfigurable, expandable semiconductor integrated circuit A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing a... | 07/13/2006 |
| 20060155955 | SIMD-RISC processor module A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control pr... | 07/13/2006 |
| 20060149922 | Multiple computational clusters in processors and methods thereof A processor may have more than one computational cluster. An instruction packet may include an instruction replication control word to indicate that a particular machine language instruction in the instruction packet is to be executed in parallel by two or more of the c... | 07/06/2006 |
| 20060149921 | Method and apparatus for sharing control components across multiple processing elements Method and apparatus for sharing control components across multiple processing elements. In one embodiment, common control components, including a control store and instruction control unit, are shared across multiple processing cores on a combined microengine. Each pro... | 07/06/2006 |
| 20060143428 | Semiconductor signal processing device An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred... | 06/29/2006 |
