Today In History
Theo and Wayne Hart received a patent for a ponytail hair clasp.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131306 | Streaming Translation in Display Pipe In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation ... | 05/24/2012 |
| 20110264887 | Preload instruction control A processor 4 is provided with an instruction decoder 32 responsive to preload instructions PLD [r0] which trigger preload operations, such as page table walks and cache line fetches. An instruction decoder identifies if the memory address assoc... | 10/27/2011 |
| 20110252216 | Thread-local hash table based write barrier buffers A write barrier is implemented using thread-local hash table based write barrier buffers. The write barrier, executed by mutator threads, stores addresses of written memory locations or objects in the thread-local hash tables, and during garbage collection, an explicit ... | 10/13/2011 |
| 20110131363 | MECHANISM FOR REMAPPING POST VIRTUAL MACHINE MEMORY PAGES According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor... | 06/02/2011 |
| 20110040941 | Microprocessor with Improved Data Stream Prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/... | 02/17/2011 |
| 20100153689 | Processor instruction used to determine whether to perform a memory-related trap Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whet... | 06/17/2010 |
| 20100122062 | Using an IOMMU to Create Memory Archetypes In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory syste... | 05/13/2010 |
| 20100106936 | Calculator and TLB control method A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In t... | 04/29/2010 |
| 20090204785 | Computer with two execution modes A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, ... | 08/13/2009 |
| 20090198950 | Techniques for Indirect Data Prefetching A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The pref... | 08/06/2009 |
| 20090187727 | INDEX GENERATION FOR CACHE MEMORIES Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information assoc... | 07/23/2009 |
| 20090106523 | TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the ... | 04/23/2009 |
| 20090070545 | PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION USING A MULTIPLE PAGE PER ENTRY TRANSLATION LOOKASIDE BUFFER A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of con... | 03/12/2009 |
| 20090043985 | ADDRESS TRANSLATION DEVICE AND METHODS A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When th... | 02/12/2009 |
| 20080270738 | Virtual address hashing Embodiments include methods, apparatus, and systems for virtual address hashing. One embodiment evenly distributes page-table entries throughout a hash table so applications do not generate a same hash index for mapping virtual addresses to physical addresses.... | 10/30/2008 |
| 20080256282 | Calibration of Read/Write Memory Access via Advanced Memory Buffer Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data b... | 10/16/2008 |
| 20080184006 | Method and System for Preloading Page Using Control Flow A method and system for page preloading using a control flow are provided. The method includes extracting preload page information from one or more pages in a first program code, and generating a second program code including the first program code and the extracted pre... | 07/31/2008 |
| 20080172543 | Device, Method and Computer Program Product for Multi-Level Address Translation A method for retrieving information from a storage unit, the method includes: receiving, by an input output memory management unit second-level translation information representative of a partition of a storage unit address space; receiving, by a input output memory man... | 07/17/2008 |
| 20080133873 | System and Method of Improved Large Page Handling in a Virtual Memory System A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receive... | 06/05/2008 |
| 20080077766 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD According to one embodiment, an information processing apparatus includes a system memory and a video memory allocated to a part of a storage area of the system memory. A storing unit stores a plurality of tables each corresponding to one of a plurality of kinds of oper... | 03/27/2008 |
| 20080046666 | SYSTEMS AND METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible v... | 02/21/2008 |
| 20070266221 | Data Recording Device and Goods-Processing Apparatus Comprising Same A data recording device is provided in which FAT and directory data, which are file managing information, are protected, whereby, during a restart, the FAT and directory data can be restored to a state that was in effect directly before a file update or another file ope... | 11/15/2007 |
| 20070033540 | Systems and methods for directory and file manipulation using a multifunction device A method and system of rendering a graphical user interface of a multifunction device. In an embodiment, the method comprises displaying, by the multifunction device, a graphical user interface including a plurality of user-selectable elements. The user-selectable eleme... | 02/08/2007 |
| 20060271759 | Translation information retrieval A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory managem... | 11/30/2006 |
| 20060259735 | System and method of improved large page handling in a virtual memory system A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receive... | 11/16/2006 |
| 20060230252 | System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memor... | 10/12/2006 |
| 20060224815 | Virtualizing memory management unit resources In one embodiment, the present invention includes a method of intercepting a guest software execution of a translation insertion operation, and performing the translation insertion operation using host software. For example, the host software may obtain a requested tran... | 10/05/2006 |
| 20060212675 | Method and system for optimizing translation lookaside buffer entries A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic confi... | 09/21/2006 |
| 20060206686 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for... | 09/14/2006 |
| 20060200644 | Storage medium for storing processing mode specifying information conversion program and processing mode specifying information conversion method The present invention provides a processing mode specifying information conversion method. The method includes: acquiring first information for specifying a processing mode of a first process in a first program by acquiring means, converting the acquired first informati... | 09/07/2006 |
| 20060195677 | Bank conflict avoidance in a multi-banked cache system A cache system comprises a plurality of cache banks, a translation look-aside buffer (TLB), and a scheduler. The TLB is used to translate a virtual address (VA) to a physical address (PA). The scheduler, before the VA has been completely translated to the PA, uses a sub... | 08/31/2006 |
| 20060174053 | Method and apparatus for supporting address translation in a virtual machine environment In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The... | 08/03/2006 |
| 20060161760 | Multiple contexts for efficient use of translation lookaside buffer The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded proce... | 07/20/2006 |
| 20060112256 | Method and apparatus for address mapping A method and apparatus for address mapping are provided, wherein the method sets a first address region that is accessible by a processor when a system is booted and a second address region that is expanded by a virtual address, respectively. The first and second addres... | 05/25/2006 |
| 20060101227 | Method and apparatus for sharing TLB entries A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may acce... | 05/11/2006 |
