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| Application No. | Application Title | Issue Date |
| 20110179245 | INDEPENDENT LINK AND BANK SELECTION Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to... | 07/21/2011 |
| 20110167238 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules acc... | 07/07/2011 |
| 20100228939 | Parallel Read Functional Unit for Microprocessors A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and se... | 09/09/2010 |
| 20100223443 | MULTI-PROTOCOL ACCESS TO FILES AND DIRECTORIES An operating system is provided. The system includes an agent component to monitor computer activities between one or more single-item access components and one or more set-based access components. A protocol component is employed by the agent component to mitigate data... | 09/02/2010 |
| 20100199057 | INDEPENDENT LINK AND BANK SELECTION Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to... | 08/05/2010 |
| 20100180096 | LICENSE DATA FOR CONTROLLING PARTIAL AVOIDANCE OR SIMULTANEOUS ACCESS TO MULTIMEDIA CONTENTS, AND APPARATUS AND METHOD FOR CONSUMING MULTIMEDIA CONTENTS USING THIS LICENSE DATA Provided is a technology for controlling partial avoidance or simultaneous access to multimedia contents. This research provides a multimedia contents consuming apparatus, which includes: a receiver for receiving a multimedia content and license data representing a cond... | 07/15/2010 |
| 20100174856 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store... | 07/08/2010 |
| 20100088484 | SYNCHRONOUS FLASH MEMORY WITH STATUS BURST OUTPUT A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external... | 04/08/2010 |
| 20100030993 | Memory Access Control Device, Memory Access Control Method, Data Storage Method and Memory Access Control Program An access control device which increases memory access efficiency to data stored in a memory according to the present invention comprises a plurality of groups of the memory, divides and stores the data in different memory areas of the plurality of groups of the memory ... | 02/04/2010 |
| 20090300271 | STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORIES, AND CONTROLLER AND ACCESS METHOD THEREOF A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enable... | 12/03/2009 |
| 20090228615 | Vehicle Computer System with Audio Entertainment System A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to t... | 09/10/2009 |
| 20090228674 | DISK ARRAY APPARATUS FOR CONTROLLING START TIMING OF DISK DRIVE To realize a disk array device which suppresses vibrations during HDD spinning-up, there is provided a disk array apparatus, comprising: a plurality of disk drives; and a controller for controlling the plurality of disk drives, the disk array apparatus controlling power... | 09/10/2009 |
| 20090204780 | DATA STORAGE UNIT, DATA STORAGE CONTROLLING APPARATUS AND METHOD, AND DATA STORAGE CONTROLLING PROGRAM A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage con... | 08/13/2009 |
| 20090198847 | Serial memory interface A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured ... | 08/06/2009 |
| 20090157994 | MEMORY MODULE WITH REDUCED ACCESS GRANULARITY A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and... | 06/18/2009 |
| 20090125785 | Pipelined Data Relocation and Improved Chip Architectures The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior ... | 05/14/2009 |
| 20090077337 | DATA READING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a... | 03/19/2009 |
| 20090049254 | MEMORY CONTROLLER AND PROCESSOR SYSTEM A memory controller includes a memory diagnosing part for controlling access from a CPU to a memory, and accessing and diagnosing the memory, an information setting part for setting cycle information according to a loaded condition of the CPU, and a cycle adjusting part... | 02/19/2009 |
| 20090013144 | INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT SYSTEM A main LSI includes a plurality of master circuits that transmit access requests to an SDRAM, an input interface that receives an access request from a master circuit in a sub LSI, an arbitration circuit that receives the access requests from the internal master circuit... | 01/08/2009 |
| 20080320249 | FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.... | 12/25/2008 |
| 20080301392 | SYSTEM AND DEVICE HAVING ALTERNATIVE BIT ORGANIZATION A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is co... | 12/04/2008 |
| 20080270727 | Data transfer in cluster storage systems Embodiments include methods, apparatus, and systems for data transfer in storage systems. One embodiment includes a method that transmits a state of cached write data and mapping metadata associated with a disk group from a first array to a second array and then transfe... | 10/30/2008 |
| 20080263303 | LINEAR COMBINER WEIGHT MEMORY A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight va... | 10/23/2008 |
| 20080244209 | METHODS AND DEVICES FOR DETERMINING QUALITY OF SERVICES OF STORAGE SYSTEMS Methods and systems for allowing access to computer storage systems. Multiple requests from multiple applications can be received and processed efficiently to allow traffic from multiple customers to access the storage system concurrently.... | 10/02/2008 |
| 20080140975 | Contention detection with data consolidation A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same... | 06/12/2008 |
| 20080140976 | Advanced contention detection A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same... | 06/12/2008 |
| 20080133862 | Contention detection with modified message format A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same... | 06/05/2008 |
| 20070266201 | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memor... | 11/15/2007 |
| 20070239955 | Memory Scoreboard Embodiments of a memory scoreboard are presented herein. ... | 10/11/2007 |
| 20070198770 | Memory system and memory card A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which c... | 08/23/2007 |
| 20070162719 | Apparatus and method to switch a FIFO between strobe sources A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to... | 07/12/2007 |
| 20070150687 | Memory system with both single and consolidated commands In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in respon... | 06/28/2007 |
| 20070150688 | Chips providing single and consolidated commands In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode... | 06/28/2007 |
| 20070130438 | Atomic operation involving processors with different memory transfer operation sizes Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containin... | 06/07/2007 |
| 20070113034 | Storage remote copy system In the conventional storage system, consistency is ensured only for writing from a single storage. Asynchronous remote copying and local replication are also alternately suspended in the conventional system, so that the suspension time increases and the volume in which ... | 05/17/2007 |
| 20070113038 | PROCESSOR CLUSTER ARCHITECTURE AND ASSOCIATED PARALLEL PROCESSING METHODS A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assign... | 05/17/2007 |
| 20070094460 | DRAM control circuit A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detectin... | 04/26/2007 |
| 20070050565 | Storage system Embodiments of the present invention are directed to methods and systems of storing data in storage volumes while ensuring data matching between the storage volumes. In one embodiment, a system for storing data comprises a first storage area to store data, a second stor... | 03/01/2007 |
| 20070022264 | Maintaining write order fidelity on a multi-writer system Write order fidelity (WOF) is maintained for totally-active implementations wherein a plurality of access nodes at geographically separated sites can concurrently read and/or write data in a “totally active” fashion on a distributed data system. From the hosts' pers... | 01/25/2007 |
| 20060294333 | Managing message queues A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, determ... | 12/28/2006 |
