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| Application No. | Application Title | Issue Date |
| 20120054456 | MIGRATING AN ENCODED DATA SLICE BASED ON AN END-OF-LIFE MEMORY LEVEL OF A MEMORY DEVICE A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues with the processing module determining an end-of-life memory level for the memory device. The method continues with the pr... | 03/01/2012 |
| 20120017055 | Method and device for scheduling queues based on chained list The present invention discloses a method for scheduling queues based on a chained list. The method includes the following steps: setting the number of addresses in a queuing chained list not less than the number of queues, and partitioning the queuing chained list into ... | 01/19/2012 |
| 20120005439 | COMPUTER SYSTEM HAVING A CACHE MEMORY AND CONTROL METHOD OF THE SAME A computer includes a memory that stores data, a cache memory that stores a copy of the data, a directory storage unit that stores directory information related to the data and includes information indicating that the data is copied to the cache memory, a directory cach... | 01/05/2012 |
| 20110271277 | METHOD AND APPARATUS FOR A VIRTUAL SYSTEM ON CHIP A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurali... | 11/03/2011 |
| 20110264873 | External Memory Controller A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to f... | 10/27/2011 |
| 20110238934 | ASYNCHRONOUSLY SCHEDULING MEMORY ACCESS REQUESTS A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The s... | 09/29/2011 |
| 20110213917 | Methods and Systems for Improving Read Performance in Data De-Duplication Storage The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a data de-duplication system that retrieves data ... | 09/01/2011 |
| 20110213938 | SIMULTANEOUS PERSONAL SENSING AND DATA STORAGE A personal sensing device that may be used for storing personal data and sensed data arbitrates and prioritizes competing requests for memory access from sensing, wireless, and wired interfaces. The personal sensing device enables power efficiency with burst-writes to t... | 09/01/2011 |
| 20110208926 | LOW LATENCY REQUEST DISPATCHER A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the ... | 08/25/2011 |
| 20110197038 | SERVICING LOW-LATENCY REQUESTS AHEAD OF BEST-EFFORT REQUESTS The invention relates to a method of controlling access of a System-on-Chip to an off-chip memory, wherein the System-on-Chip comprises a plurality of agents which need access to the memory. The method comprises: i) receiving low-priority requests (CBR, BER) for access ... | 08/11/2011 |
| 20110184916 | INCREMENTAL AND PRIORITIZED RESTORATION OF BLOCKS A first computational platform generates a data structure that indicates a set of blocks, wherein the indicated set of blocks have to be rewritten to revert a logical storage structure stored in the first computational platform to a previous state. An Input/Output (I/O)... | 07/28/2011 |
| 20110185134 | TEMPORARY STATE SERVICE PROTOCOL A temporary state service protocol is utilized by clients to temporarily store and access data within a temporary data store between different requests. Each client associated with a web page can create data in the data store independently from other clients for the sam... | 07/28/2011 |
| 20110179240 | ACCESS SCHEDULER Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory... | 07/21/2011 |
| 20110131385 | DATA PROCESSING CIRCUIT WITH ARBITRATION BETWEEN A PLURALITY OF QUEUES Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a pr... | 06/02/2011 |
| 20110099341 | SYSTEM, APPARATUS, AND METHOD FOR MODIFYING THE ORDER OF MEMORY ACCESSES Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a d... | 04/28/2011 |
| 20110010512 | METHOD FOR CONTROLLING STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORY UNITS AND STORAGE SYSTEM USING THE SAME A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has ... | 01/13/2011 |
| 20100325375 | DATA-ACCESS CONTROL DEVICE AND DATA-ACCESS CONTROL METHOD A memory control unit sequentially performs access requests to a plurality of banks A to D for a high-speed module 1 according to settings of the high-speed module, and subsequently performs an access request to a bank for a low-speed module after completion of a... | 12/23/2010 |
| 20100238937 | HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port... | 09/23/2010 |
| 20100199025 | MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memo... | 08/05/2010 |
| 20100146163 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a s... | 06/10/2010 |
| 20100138618 | Priority Encoders A priority encoder and a processing device having the priority encoder. The priority encoder includes a port selector for generating a plurality of prioritized read requests based on a plurality of write requests from a plurality of processing devices and a predetermine... | 06/03/2010 |
| 20100100670 | Out of Order Dram Sequencer Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detect... | 04/22/2010 |
| 20100095049 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map ... | 04/15/2010 |
| 20100023712 | Storage subsystem and method of executing commands by controller A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of t... | 01/28/2010 |
| 20100023653 | SYSTEM AND METHOD FOR ARBITRATING BETWEEN MEMORY ACCESS REQUESTS A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the... | 01/28/2010 |
| 20090327624 | INFORMATION PROCESSING APPARATUS, CONTROLLING METHOD THEREOF, AND PROGRAM An information processing apparatus controls writing to a disk. A command reception section receives from a host apparatus a write command and a control command controlling a cache about the write command. A queue storage section stores a queue for the write command and... | 12/31/2009 |
| 20090292886 | REACTIVE PLACEMENT CONTROLLER FOR INTERFACING WITH BANKED MEMORY STORAGE An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is include... | 11/26/2009 |
| 20090248999 | MEMORY CONTROL APPARATUS, MEMORY CONTROL METHOD AND INFORMATION PROCESSING SYSTEM A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a storage unit, by a first port in which the received fetch response data can be s... | 10/01/2009 |
| 20090240902 | Computer system and command execution frequency control method A computer system of the present invention can adjust the execution frequencies of a command issued from a host and a command issued from a storage. An external manager disposed in the host configures a priority for a host command issued from a command issuing module in... | 09/24/2009 |
| 20090216917 | DEVICE AND METHOD FOR ARBITRATING BETWEEN DIRECT MEMORY ACCESS TASK REQUESTS A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated wi... | 08/27/2009 |
| 20090193204 | SYSTEM AND METHOD OF ACCESSING MEMORY WITHIN AN INFORMATION HANDLING SYSTEM A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation o... | 07/30/2009 |
| 20090193203 | System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a... | 07/30/2009 |
| 20090177853 | SYSTEM AND METHODS FOR MEMORY EXPANSION This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may al... | 07/09/2009 |
| 20090172264 | SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with ... | 07/02/2009 |
| 20090172316 | MULTI-LEVEL PAGE-WALK APPARATUS FOR OUT-OF-ORDER MEMORY CONTROLLERS SUPPORTING VIRTUALIZATION TECHNOLOGY The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention... | 07/02/2009 |
| 20090172315 | PRIORITY AWARE SELECTIVE CACHE ALLOCATION A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probab... | 07/02/2009 |
| 20090164741 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD An information processing apparatus and an information processing method are capable of correctly selecting data to be deleted, without a user having to perform a troublesome operation. In a backup operation, a determination is made for each image file as to whether a p... | 06/25/2009 |
| 20090164740 | DEVICE AND METHOD FOR EXTRACTING MEMORY DATA A device and method for extracting data stored in a volatile memory are provided. In particular, a memory-data extracting device and method for ensuring integrity of data extracted from a volatile memory installed in a computer are provided. A memory-data extracting mod... | 06/25/2009 |
| 20090083501 | CANCELLATION OF INDIVIDUAL LOGICAL VOLUMES IN PREMIGRATION CHAINS Provided are techniques for cancellation of premigration of a member in a chain. A set of premigration messages are received, wherein a separate premigration message is received for each logical volume in a chain of logical volumes. While processing the premigration mes... | 03/26/2009 |
| 20090049256 | MEMORY CONTROLLER PRIORITIZATION SCHEME A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first... | 02/19/2009 |
