Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Application No. | Application Title | Issue Date |
| 20120131266 | MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile me... | 05/24/2012 |
| 20120127805 | MEMORY ELEMENTS HAVING SHARED SELECTION SIGNALS Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read sele... | 05/24/2012 |
| 20120131275 | NETWORK-ATTACHED STORAGE SYSTEM The invention discloses a network-attached storage system including an interface module, a plurality of storage devices and a storage module. The interface module is configured to be attached to a network. The interface module is for receiving a transmission protocol in... | 05/24/2012 |
| 20120131287 | STORAGE CONTROL APPARATUS AND LOGICAL VOLUME SIZE SETTING METHOD The present invention efficiently changes a volume size while maintaining a copy pair as-is. A PVOL and a SVOL #1 are in a pair state and are synchronized. The PVOL and a SVOL #2 are in a restore state. Upon instruction of expansion of the size of the PVOL... | 05/24/2012 |
| 20120131288 | Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each co... | 05/24/2012 |
| 20120131286 | DYNAMIC DETECTION AND REDUCTION OF UNALIGNED I/O OPERATIONS Detection and reduction of unaligned input/output (“I/O”) requests is implemented by a storage server determining an alignment value for data stored by the server within a storage system on behalf of a first client, writing the alignment value to a portion of the vo... | 05/24/2012 |
| 20120127790 | ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possi... | 05/24/2012 |
| 20120110281 | VIRTUALIZATION AND OFFLOAD READS AND WRITES Aspects of the subject matter described herein relate to virtualization and offload reads and writes. In aspects, an offload read allows a requestor to obtain a token that represents data while an offload write allows the requestor to request that the data (or a part th... | 05/03/2012 |
| 20120110278 | REMAPPING OF INOPERABLE MEMORY BLOCKS Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM... | 05/03/2012 |
| 20120110367 | Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both in... | 05/03/2012 |
| 20120110414 | Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of inf... | 05/03/2012 |
| 20120110283 | DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that... | 05/03/2012 |
| 20120110282 | SYSTEMS AND METHODS FOR MANAGING INFORMATION OBJECTS IN DYNAMIC DATA STORAGE DEVICES According to one aspect, a system for managing information objects in dynamic data storage devices including a first data storage device having a plurality of information objects, a second data storage device operatively connectable to an output device for providing at ... | 05/03/2012 |
| 20120110280 | OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE The present invention provides a method and apparatus for supporting embodiments of an out-of-order load/store queue structure. One embodiment of the apparatus includes a first queue for storing memory operations adapted to be executed out-of-order with respect to other... | 05/03/2012 |
| 20120110279 | METHOD AND SYSTEM FOR NON-DISRUPTIVE MIGRATION Method and system for migrating a virtual storage system from a source storage system having access to a source storage device to a destination storage system having access to a destination storage device is provided. A processor executable management application estima... | 05/03/2012 |
| 20120110284 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND PROGRAM The present invention relates to a data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. A read/write control portion 73 executes... | 05/03/2012 |
| 20120110277 | METHOD AND SYSTEM FOR STORAGE-SYSTEM MANAGEMENT One example of the present invention is directed to a data-storage system comprising a plurality of data-storage devices, one or more communications connections through which the data-storage system receives management and data-access commands and sends responses to rec... | 05/03/2012 |
| 20120110309 | Data Output Transfer To Memory Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a me... | 05/03/2012 |
| 20120084493 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.... | 04/05/2012 |
| 20120072680 | SEMICONDUCTOR MEMORY CONTROLLING DEVICE According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used fo... | 03/22/2012 |
| 20120072679 | Reordering in the Memory Controller In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS param... | 03/22/2012 |
| 20120072647 | Different types of memory integrated in one chip by using a novel protocol A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-... | 03/22/2012 |
| 20120072681 | MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory c... | 03/22/2012 |
| 20120072682 | DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode dete... | 03/22/2012 |
| 20120072678 | Dynamic QoS upgrading In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS param... | 03/22/2012 |
| 20120054427 | INCREASING DATA ACCESS PERFORMANCE Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub... | 03/01/2012 |
| 20120054454 | SAMPLING FREQUENCY CONVERTER A sampling frequency converter has a buffer that stores data in response to a write request signal, and outputs stored data in order from the oldest data in response to a read request signal. An interpolation unit sequentially receives data from an external source, perf... | 03/01/2012 |
| 20120054453 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM An information processing apparatus includes: a main memory apparatus capable of storing one or more programs read and processed by a central processing unit and holding stored contents by securing an energized state even under suspension of a system; a nonvolatile stor... | 03/01/2012 |
| 20120054436 | SYSTEM AND METHOD FOR CACHE MANAGEMENT IN A DIF ENABLED STORAGE SYSTEM A system and method for caching file data is disclosed. In one embodiment, in a method for caching file data stored in a storage device, wherein the file data is used by an application running on a computing system having a processor, a file system residing in memory, a... | 03/01/2012 |
| 20120054437 | INCREASING DATA ACCESS PERFORMANCE Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub... | 03/01/2012 |
| 20120054306 | ERROR HANDLING METHODS FOR VIRTUALIZED COMPUTER SYSTEMS EMPLOYING SPACE-OPTIMIZED BLOCK DEVICES Interfaces to storage devices that employ storage space optimization technologies, such as thin provisioning, are configured to enable the benefits gained from such technologies to be sustained. Such an interface may be provided in a hypervisor of a virtualized computer... | 03/01/2012 |
| 20120054435 | STORING THE MOST SIGNIFICANT AND THE LEAST SIGNIFICANT BYTES OF CHARACTERS AT NON-CONTIGUOUS ADDRESSES In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first le... | 03/01/2012 |
| 20120054452 | Smart Memory An apparatus comprising a storage device comprising a plurality of memory tiles each comprising a memory block and a processing element, and an interconnection network coupled to the storage device and configured to interconnect the memory tiles, wherein the processing ... | 03/01/2012 |
| 20120047336 | METHOD OF VERIFYING SYSTEM PERFORMANCE AND PERFORMANCE MEASUREMENT APPARATUS A computer-readable, non-transitory medium storing a program for measuring a performance in a system including a storage unit and a plurality of control units for controlling an access to the storage unit, the program causing a computer to execute a procedure, the proce... | 02/23/2012 |
| 20120047338 | SWITCHING VISIBILITY BETWEEN VIRTUAL DATA STORAGE ENTITIES Various embodiments for switching visibility between virtual data storage entities in a data storage environment using a processor device are provided. Visibility of a data storage entity on a first storage system is switched to a replicated data storage entity on a sec... | 02/23/2012 |
| 20120047260 | Data Synchronization For Circuit Resources Without Using A Resource Buffer A resource synchronizer synchronizes transmission of data to a SerDes of a device so that the SerDes is capable of providing the data to a resource of the device without buffering the data between the SerDes and the resource.... | 02/23/2012 |
| 20120047410 | STORAGE DEVICE, CIRCUIT BOARD, LIQUID RESERVOIR AND SYSTEM A storage device according to some aspects of the invention includes a communication unit configured to perform processing for communication with a host apparatus; a storage unit configured to have a first memory area and a second memory area that store therein received... | 02/23/2012 |
| 20120047335 | LOGIC VERIFYING APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH LOGIC VERIFYING PROGRAM IS STORED A logic verifying apparatus includes a second processor corresponding to a first processor to be verified; and one or more second controllers corresponding to first controllers to be verified, the number of which is less than that of the first controllers, control a sec... | 02/23/2012 |
| 20120042135 | Flexible Microprocessor Register File Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed ... | 02/16/2012 |
| 20120042134 | METHOD AND SYSTEM FOR CIRCUMVENTING USAGE PROTECTION APPLICABLE TO ELECTRONIC MEDIA A method for bypassing a compliance mechanism assertion of a usage restriction applicable to electronic media accessible in a computer system is described. The method includes a hardware device for causing the computer system to bypass the usage restriction, the hardwar... | 02/16/2012 |
