Bizarre Patents
An enclosure for small animals which is wearable on the front or back of an animate being.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131285 | LOCKING AND SIGNALING FOR IMPLEMENTING MESSAGING TRANSPORTS WITH SHARED MEMORY Disclosed are systems and methods for transporting data using shared memory comprising allocating, by one of a plurality of sender application, one or more pages, wherein the one or more pages are stored in a shared memory, wherein the shared memory is partitioned into ... | 05/24/2012 |
| 20120110272 | CROSS PROCESS MEMORY MANAGEMENT A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using threads to communicate that additional memory is needed. If the request indica... | 05/03/2012 |
| 20120110271 | MECHANISM TO SPEED-UP MULTITHREADED EXECUTION BY REGISTER FILE WRITE PORT REALLOCATION Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register fi... | 05/03/2012 |
| 20120072676 | SELECTIVE MEMORY COMPRESSION FOR MULTI-THREADED APPLICATIONS A method, system, and computer usable program product for selective memory compression for multi-threaded applications are provided in the illustrative embodiments. An identification of a memory region that is shared by a plurality of threads in an application is receiv... | 03/22/2012 |
| 20120047390 | APPARATUS AND METHOD OF CONTROLLING A PROCESSOR CLOCK FREQUENCY An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses co... | 02/23/2012 |
| 20120039404 | SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data... | 02/16/2012 |
| 20120030433 | Method, Mobile Terminal and Computer Program Product for Sharing Storage Device The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile storage device. A processing capacity of the first processor is different from... | 02/02/2012 |
| 20120030432 | SYSTEMS AND METHODS FOR SHARING MEDIA IN A COMPUTER NETWORK A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; c... | 02/02/2012 |
| 20120023296 | Recording Dirty Information in Software Distributed Shared Memory Systems A page table entry dirty bit system may be utilized to record dirty information for a software distributed shared memory system. In some embodiments, this may improve performance without substantially increasing overhead because the dirty bit recording system is already... | 01/26/2012 |
| 20120017029 | SHARING MEMORY SPACES FOR ACCESS BY HARDWARE AND SOFTWARE IN A VIRTUAL MACHINE ENVIRONMENT Example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method involves enabling a sharing of a memory page of a source domain executing on a f... | 01/19/2012 |
| 20120005434 | SEMICONDUCTOR MEMORY APPARATUS A semiconductor memory apparatus includes a data selection unit, a first data processing unit, and a second data processing unit. The data selection unit is configured to select one of the first and second transfer lines to be coupled to a data pad in response to addres... | 01/05/2012 |
| 20120005401 | PAGE BUFFERING IN A VIRTUALIZED, MEMORY SHARING CONFIGURATION An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtu... | 01/05/2012 |
| 20110320741 | METHOD AND APPARATUS PROVIDING FOR DIRECT CONTROLLED ACCESS TO A DYNAMIC USER PROFILE An apparatus may include a profile determiner configured to determine a user profile. A contextual characteristic determiner may be configured to determine contextual characteristics relating to the apparatus and/or the user of the apparatus such that the profile determ... | 12/29/2011 |
| 20110320719 | PROPAGATING SHARED STATE CHANGES TO MULTIPLE THREADS WITHIN A MULTITHREADED PROCESSING ENVIRONMENT A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications net... | 12/29/2011 |
| 20110314338 | DATA COLLISIONS IN CONCURRENT PROGRAMS Described are techniques for detecting data collisions between a first portion and a second portion of an application executing on a computer, the first portion and the second portions executing concurrently with respect to each other. While the first portion and second... | 12/22/2011 |
| 20110314469 | METHOD FOR NETWORK INTERFACE SHARING AMONG MULTIPLE VIRTUAL MACHINES In a computing system, sharing a physical NIC device among multiple virtual machines may be implemented by a customer virtual machine by receiving, by a virtual network interface card (NIC) driver of a customer operating system (OS) running in the customer virtual machi... | 12/22/2011 |
| 20110307665 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.... | 12/15/2011 |
| 20110307669 | SHARED MEMORY ARCHITECTURE A shared memory architecture is disclosed to support operations associated with executing shared functions from a shared memory space in such a manner that separate pieces of software can execute the shared functions.... | 12/15/2011 |
| 20110307614 | Techniques For Efficient Remote Presentation Session Connectivity And Routing Techniques are disclosed for efficient remote presentation session connectivity and routing. In an embodiment, the roles of a remote presentation session deployment involved in receiving a connection from a client and determining a virtual machine (VM) to serve the clie... | 12/15/2011 |
| 20110307668 | METHOD AND SYSTEM OF UPDATING SHARED MEMORY A method and system is disclosed for updating a shared memory or other memory location where multiple entities rely on code stored to the same memory to support one or more operation functions. The shared memory may be updated such that the code intended to the replace ... | 12/15/2011 |
| 20110302377 | Automatic Reallocation of Structured External Storage Structures A mechanism for automatic reallocation of shared external storage structures is provided. The shared external storage divides the dynamically allocable storage into fixed sized blocks referred to as allocation units. To create an object of a specific type, the shared ex... | 12/08/2011 |
| 20110302375 | Multi-Part Aggregated Variable in Structured External Storage A mechanism is provided for multi-part aggregated variables in structured external storage. The shared external storage provides a serialized, aggregated structure update capability. The shared external storage identifies each local value for which a group value is need... | 12/08/2011 |
| 20110271060 | Method And System For Lockless Interprocessor Communication A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive, from a first processor, a message to be sent to a second processor; store the message in a portion of a shared memory, the shared ... | 11/03/2011 |
| 20110271059 | REDUCING REMOTE READS OF MEMORY IN A HYBRID COMPUTING ENVIRONMENT A hybrid computing environment in which the host computer allocates, in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator; writes packet data to the accelerator's shared memory in a memory regi... | 11/03/2011 |
| 20110264867 | MULTIPROCESSOR COMPUTING SYSTEM WITH MULTI-MODE MEMORY CONSISTENCY PROTECTION Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, an... | 10/27/2011 |
| 20110264841 | SHARING OF CLASS DATA AMONG VIRTUAL MACHINE APPLICATIONS RUNNING ON GUESTS IN VIRTUALIZED ENVIRONMENT USING MEMORY MANAGEMENT FACILITY A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized environment. A control program in a virtual operating system is used to manage the user portions of the virtual operati... | 10/27/2011 |
| 20110258353 | Bus Arbitration Techniques to Reduce Access Latency A method of arbitrating requests from bus masters for access to shared memory in order to reduce access latency, comprises looking ahead into currently scheduled requests to the shared memory and predicting latency of the requests based on characteristics of the current... | 10/20/2011 |
| 20110258245 | Performing A Local Reduction Operation On A Parallel Computer A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an input buffer. Copying, in interleaved chunks by the reduction processing cor... | 10/20/2011 |
| 20110252200 | COHERENT MEMORY SCHEME FOR HETEROGENEOUS PROCESSORS Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage r... | 10/13/2011 |
| 20110252258 | HARDWARE ACCELERATION APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM EFFICIENTLY PROCESSING MULTI-CORE SYNCHRONIZATION Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Ad... | 10/13/2011 |
| 20110246727 | System and Method for Tracking References to Shared Objects Using Byte-Addressable Per-Thread Reference Counters The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counte... | 10/06/2011 |
| 20110246725 | System and Method for Committing Results of a Software Transaction Using a Hardware Transaction The system and methods described herein may exploit hardware transactional memory to improve the performance of a software or hybrid transactional memory implementation, even when an entire user transaction cannot be executed within a hardware transaction. The user code... | 10/06/2011 |
| 20110246724 | System and Method for Providing Locale-Based Optimizations In a Transactional Memory The system and methods described herein may reduce read/write fence latencies and cache pressure related to STM metadata accesses. These techniques may leverage locality information (as reflected by the value of a respective locale guard) associated with each of a plura... | 10/06/2011 |
| 20110246993 | System and Method for Executing a Transaction Using Parallel Co-Transactions The transactional memory system described herein may implement parallel co-transactions that access a shared memory such that at most one of the co-transactions in a set will succeed and all others will fail (e.g., be aborted). Co-transactions may improve the performanc... | 10/06/2011 |
| 20110246726 | PROCESSING DATA IN SHARED MEMORY Various embodiments of systems and methods for processing data in shared memory are described herein. A number of work processes of an application server write data in corresponding areas of shared memory. At least one data unit for a first process is read from a first ... | 10/06/2011 |
| 20110239003 | Direct Injection of Data To Be Transferred In A Hybrid Computing Environment Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. ... | 09/29/2011 |
| 20110239219 | PROTECTING SHARED RESOURCES USING SHARED MEMORY AND SOCKETS Shared memory and sockets are used to protect shared resources in an environment where multiple operating systems execute concurrently on the same hardware. Rather than using spinlocks for serializing access to the shared resources, when a thread is unable to acquire a ... | 09/29/2011 |
| 20110231616 | DATA PROCESSING METHOD AND SYSTEM A configurable multi-core structure is provided for executing a program. The configurable multi-core structure includes a plurality of processor cores and a plurality of configurable local memory respectively associated with the plurality of processor cores. The configu... | 09/22/2011 |
| 20110213936 | PROCESSOR, MULTIPROCESSOR SYSTEM, AND METHOD OF DETECTING ILLEGAL MEMORY ACCESS A processor included in a multiprocessor system including a shared memory, the processor according to an embodiment of the present invention comprises: a storing unit that stores a break occurrence memory area that is address information of the shared memory; and a brea... | 09/01/2011 |
| 20110214123 | Mechanism for Optimal Placement of Virtual Machines to Reduce Memory Consumption Based on Shared Images A mechanism for optimal placement of VMs based on shared images is disclosed. A method of embodiments of the invention includes identifying a virtual machine (VM) image of a new VM to be placed by a host controller on one of a plurality of candidate host machines, for e... | 09/01/2011 |
