Class 711/146 - Snooping

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter further comprising cache memory monitoring
No. of applications: 266
Last issue date: 05/24/2012

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Application No.	Application Title	Issue Date
20120131284	MULTI-CORE ACTIVE MEMORY PROCESSOR SYSTEM In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originati...	05/24/2012
20120110396	Error handling mechanism for a tag memory within coherency control circuitry A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14,...	05/03/2012
20120110270	DATA PROCESSING SYSTEM HAVING SELECTIVE INVALIDATION OF SNOOP REQUESTS AND METHOD THEREFOR A data processing system includes a system interconnect, a processor coupled to the system interconnect, and a cache coherency manager (CCM) coupled to the system interconnect. The processor includes a cache. A method includes generating, by the CCM, one or more snoop r...	05/03/2012
20120054450	BALANCING LOADS OF A PLURALTY OF BUS LANES OF A SNOOPING-BASED BUS A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an an...	03/01/2012
20120047333	EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the infor...	02/23/2012
20120036328	DYNAMIC CACHE REDUCTION UTILIZING VOLTAGE WARNING MECHANISM An interface controller of a storage device configured to manage a write cache of the storage device responsive to changes in a voltage supply provided to the storage device. In one implementation, the interface controller reduces the size of the write cache responsive ...	02/09/2012
20110296115	Assigning Memory to On-Chip Coherence Domains A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running...	12/01/2011
20110296116	System and Method for Aggregating Core-Cache Clusters in Order to Produce Multi-Core Processors According to one embodiment of the invention, a processor comprises a memory, a plurality of core-cache clusters and a scalability agent unit that operates as an interface between an on-die interconnect and multiple core-cache clusters. The scalability agent operates in...	12/01/2011
20110213934	Data processing apparatus and method for switching a workload between first and second processing circuitry A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the f...	09/01/2011
20110213993	Data processing apparatus and method for transferring workload between source and destination processing circuitry In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the tr...	09/01/2011
20110213935	Data processing apparatus and method for switching a workload between first and second processing circuitry A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the f...	09/01/2011
20110197033	Cache Used Both as Cache and Staging Buffer In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a...	08/11/2011
20110191543	Area and power efficient data coherency maintenance An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for mo...	08/04/2011
20110191546	MEMORY ACCESS PREDICTION An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, a...	08/04/2011
20110185128	Memory access method and information processing apparatus To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs duri...	07/28/2011
20110161601	INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDANCE IN A RETRY BASED PIPELINE Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including loca...	06/30/2011
20110153924	CORE SNOOP HANDLING DURING PERFORMANCE STATE AND POWER STATE TRANSITIONS IN A DISTRIBUTED CACHING AGENT A method and apparatus may provide for detecting a performance state transition in a processor core and bouncing a core snoop message on a shared interconnect ring in response to detecting the performance state transition. The core snoop message may be associated with t...	06/23/2011
20110153956	Cache Coherent Switch Device In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. T...	06/23/2011
20110153955	SOFTWARE ASSISTED TRANSLATION LOOKASIDE BUFFER SEARCH MECHANISM A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified transl...	06/23/2011
20110145530	LEVERAGING MEMORY ISOLATION HARDWARE TECHNOLOGY TO EFFICIENTLY DETECT RACE CONDITIONS One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread on...	06/16/2011
20110138124	TRACE MODE FOR CACHE MEMORY SYSTEM A cache, including a cache memory, is configurable to operate in a cache mode and a trace mode. When the cache is operating in the cache mode, the cache memory stores a copy of a portion of data that is stored in another memory external to the cache, and a received data...	06/09/2011
20110138132	RESCINDING OWNERSHIP OF A CACHE LINE IN A COMPUTER SYSTEM A method of rescinding ownership of a cache line in a computer system includes constructing a table of caching agent representations in which each caching agent representation is accompanied by a validity indicator. The method continues with receiving a cache line shari...	06/09/2011
20110078384	MEMORY MIRRORING AND MIGRATION AT HOME AGENT Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are...	03/31/2011
20110078492	HOME AGENT DATA AND MEMORY MANAGEMENT Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location....	03/31/2011
20110040911	DUAL INTERFACE COHERENT AND NON-COHERENT NETWORK INTERFACE CONTROLLER ARCHITECTURE A dual interface coherent and non-coherent network interface controller architecture is generally presented. In this regard, a network interface controller is introduced including a non-coherent bus interface to communicatively couple with devices of a system through a ...	02/17/2011
20110010501	EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and,...	01/13/2011
20110004731	CACHE MEMORY DEVICE, CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM A cache memory device includes: a storage unit in which data and attribute information can be stored in association with each other; and a cache controller which (i) obtains, from CPU, a request signal requesting access to data and an indication signal indicating whethe...	01/06/2011
20100332762	DIRECTORY CACHE ALLOCATION BASED ON SNOOP RESPONSE INFORMATION Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy ...	12/30/2010
20100332768	FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mec...	12/30/2010
20100332767	Controllably Exiting An Unknown State Of A Cache Coherency Directory In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a...	12/30/2010
20100312970	Cache Management Through Delayed Writeback The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold ...	12/09/2010
20100312969	Methods And Apparatus For Supporting Multiple Configurations In A Multi-Processor System Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a ...	12/09/2010
20100306478	DATA CACHE WITH MODIFIED BIT ARRAY A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organiza...	12/02/2010
20100306470	Methods and Apparatus for Issuing Memory Barrier Commands in a Weakly Ordered Storage System Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory ...	12/02/2010
20100293340	Wake-and-Go Mechanism with System Bus Response A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value...	11/18/2010
20100287341	Wake-and-Go Mechanism with System Address Bus Transaction Master A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value...	11/11/2010
20100287342	PROCESSING OF COHERENT AND INCOHERENT ACCESSES AT A UNIFORM CACHE Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and ...	11/11/2010
20100274971	Multi-Core Processor Cache Coherence For Reduced Off-Chip Traffic Technologies are generally described herein for maintaining cache coherency within a multi-core processor. A first cache entry to be evicted from a first cache may be identified. The first cache entry may include a block of data and a first tag indicating an owned state...	10/28/2010
20100274975	Forming Multiprocessor Systems Using Dual Processors In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the M...	10/28/2010
20100275053	CLOCK SKEW MEASUREMENT FOR MULTIPROCESSOR SYSTEMS Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize a t...	10/28/2010

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Class 711/146 - Snooping