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| Application No. | Application Title | Issue Date |
| 20110296114 | ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions wit... | 12/01/2011 |
| 20110276765 | System and Method for Management of Cache Configuration Systems and methods for managing cache configurations are disclosed. In accordance with a method, a system management control module may receive access rights of a host to a logical storage unit and may also receive a desired caching policy for caching data associated w... | 11/10/2011 |
| 20110252203 | TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidati... | 10/13/2011 |
| 20110238927 | CONTENTS DISTRIBUTION DEVICE , CONTENTS DISTRIBUTION CONTROL METHOD, CONTENTS DISTRIBUTION CONTROL PROGRAM AND CACHE CONTROL DEVICE Solved is a problem that use efficiency of a memory cache is low because in contents distribution using a memory cache whose capacity is limited, even when only a part of contents is accessed, the entire contents will be stored in the memory cache. | 09/29/2011 |
| 20110225373 | COMPUTER SYSTEM AND METHOD OF DATA CACHE MANAGEMENT A computer system including: a file server, cache servers, and a cache management server, wherein: the cache server obtains the authority information from the cache management server, in a case of receiving a command to process a file, wherein the cache server refers to... | 09/15/2011 |
| 20100153658 | Deadlock Avoidance By Marking CPU Traffic As Special Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 06/17/2010 | |
| 20100146214 | METHOD AND SYSTEM FOR EFFICIENT CACHE LOCKING MECHANISM Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized... | 06/10/2010 |
| 20100125707 | DEADLOCK AVOIDANCE DURING STORE-MARK ACQUISITION Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cac... | 05/20/2010 |
| 20100100688 | LOW-LEVEL CONDITIONAL SYNCHRONIZATION SUPPORT A low-overhead conditional synchronization instruction operates on a synchronization variable which includes a lock bit, a state specification, and bits for user-defined data. The instruction specifies the memory address of the synchronization variable and a condition. ... | 04/22/2010 |
| 20100057994 | DEVICE AND METHOD FOR CONTROLLING CACHES Device and method for controlling caches, comprising a decoder configured to decode additional information of datasets retrievable from a memory, wherein the decoded additional information is configured to control whether particular ones of the datasets are to be stored... | 03/04/2010 |
| 20090182956 | METHOD AND APPARATUS FOR IMPROVING TRANSACTIONAL MEMORY COMMIT LATENCY Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store... | 07/16/2009 |
| 20090157982 | MULTIPLE MISS CACHE Presented herein are system(s) and method(s) for a multiple miss cache. In one embodiment, there is presented a cache system for storing data. The cache comprises a plurality of data words, a plurality of first bits, and a plurality of second bits. The plurality of data... | 06/18/2009 |
| 20090144508 | PCI Express Address Translation Services Invalidation Synchronization with TCE Invalidation A PCI Express (PCIe) computer system utilizes address translation services to translate virtual addresses from I/O device adaptors to physical addresses of system memory. A combined memory controller and host bridge uses a translation agent to convert the I/O addresses ... | 06/04/2009 |
| 20090138664 | CACHE INJECTION USING SEMI-SYNCHRONOUS MEMORY COPY OPERATION A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous ... | 05/28/2009 |
| 20090132769 | STATISTICAL COUNTING FOR MEMORY HIERARCHY OPTIMIZATION Systems and methods that optimize memory allocation in hierarchical and/or distributed data storage. A memory management component facilitates a compact manner of identifying approximately how often the memory chunk is being used, to promote efficient operation of the s... | 05/21/2009 |
| 20090077540 | Atomicity Violation Detection Using Access Interleaving Invariants During execution of a program, the situation where the atomicity of a pair of instructions that are to be executed atomically is violated is identified, and a bug is detected as occurring in the program at the pair of instructions. The pairs of instructions that are to ... | 03/19/2009 |
| 20090006767 | USING EPHEMERAL STORES FOR FINE-GRAINED CONFLICT DETECTION IN A HARDWARE ACCELERATED STM A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when no ... | 01/01/2009 |
| 20090006768 | Method and Apparatus for Accessing a Split Cache Directory A method and apparatus for accessing a cache. The method includes receiving a request to access the cache. The request includes an address of requested data to be accessed. The method also includes using a first portion of the address to perform an access to a first dir... | 01/01/2009 |
| 20080256304 | Storage system and control method thereof The plurality of host systems or the plurality of applications include an insertion unit for sending the identifier. The storage controller includes an analysis unit for identifying a host system or an application based on the identifier contained in the access informat... | 10/16/2008 |
| 20080147990 | Configurable Cache for a Microprocessor A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines... | 06/19/2008 |
| 20080147989 | Lockdown control of a multi-way set associative cache memory A multi-way set associative cache memory 6 is provided with lockdown control circuitry 26, 48 for controlling portions of that cache memory to store data which is locked within the cache memory 6 (i.e. not subject to eviction). Programmable lockdown... | 06/19/2008 |
| 20080133842 | Protected cache architecture and secure programming paradigm to protect applications Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventin... | 06/05/2008 |
| 20080120472 | METHOD AND APPARATUS FOR FORWARDING STORE DATA TO LOADS IN A PIPELINED PROCESSOR Methods, systems, and computer program products for forwarding store data to loads in a pipelined processor are provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operabl... | 05/22/2008 |
| 20070277001 | Apparatus and method for reducing information leakage between processes sharing a cache Apparatus and methods for reducing information leakage between processes sharing a cache are disclosed. In one embodiment, an apparatus includes execution logic, a cache memory, and cache security logic. The execution unit is to execute a plurality of processes. The cac... | 11/29/2007 |
| 20070198781 | Methods and apparatus to implement parallel transactions Cache logic associated with a respective one of multiple processing threads executing in parallel updates corresponding data fields of a cache to uniquely mark its contents. The marked contents represent a respective read set for a transaction. For example, at an outset... | 08/23/2007 |
| 20070180199 | Cache locking without interference from normal allocations A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from ma... | 08/02/2007 |
| 20070150665 | Propagating data using mirrored lock caches A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a... | 06/28/2007 |
| 20070143549 | System and method for reducing store latency According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interco... | 06/21/2007 |
| 20070079066 | Storage device control apparatus and control method for the storage device control apparatus A storage device control apparatus includes a mounting part and an internal connection part. The mounting part can removably mount channel control unit, each with a host interface controller formed therein for receiving data I/O requests, disk control units, each with a... | 04/05/2007 |
| 20070050563 | Synchronization arbiter for proactive synchronization within a multiprocessor computer system A synchronization arbiter may be used in a computer system including one or more processors configured to request exclusive access to a given memory resource. The request may include one or more addresses associated with the memory resource. The synchronization arbiter ... | 03/01/2007 |
| 20070050561 | Method for creating critical section code using a software wrapper for proactive synchronization within a computer system A method for creating critical section code using a software wrapper includes creating a high-level expression for requesting exclusive access to one or more memory resource addresses. The high-level expression may include an ACQUIRE function call that includes one or m... | 03/01/2007 |
| 20070050562 | Method for proactive synchronization within a computer system A method for providing proactive synchronization in a computer system includes a processor requesting exclusive access to a given memory resource. The request may include one or more addresses associated with the given memory resource. The method also includes comparing... | 03/01/2007 |
| 20070050559 | Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system A method for maintaining atomicity of a sequence of instructions includes a processor requesting exclusive access to a given memory resource. The request may include executing a critical section of code having memory reference instructions each including a LOCK prefix, ... | 03/01/2007 |
| 20070050560 | Augmented instruction set for proactive synchronization within a computer system Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of... | 03/01/2007 |
| 20070043906 | Method for data set replacement in 4-way or greater locking cache A method and means are provided for increasing both the MMBR (minimum misses before replaceable) and MHBR (minimum hits before replaceable) parameters for a virtual 3-way cache, consisting of three unlocked sets, from one to two. Thus, a minimum of two accesses to the s... | 02/22/2007 |
| 20070027722 | Method and system for generating personal/individual health records A system and method for generating and/or updating a personal/individual health record. Inputs of data to the system may come from diverse sources including, but not limited to, patient questionnaires, insurance company (or other payor) claims data, hospitals, clinics a... | 02/01/2007 |
| 20060294311 | Dynamic bloom filter for caching query results Methods, systems, and machine-readable media are disclosed for searching a corpus of information by utilizing a Bloom filter for caching query results. According to one aspect of the present invention, a method of caching information from a corpus of information can inc... | 12/28/2006 |
| 20060277351 | Method and system for efficient cache locking mechanism Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized... | 12/07/2006 |
| 20060271745 | Least mean square dynamic cache-locking A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made ... | 11/30/2006 |
| 20060259705 | Cache coherency in a shared-memory multiprocessor system A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache cohe... | 11/16/2006 |
